Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 618

PCI Bus Interface
13.3.3.17 Subsystem Vendor ID Configuration Register
Figure 13-35 shows the subsystem vendor ID fields. The subsystem vendor ID configuration register is
read-only from the PCI bus, but it can be programmed from the CSB.
Offset 0x2C
15
R
W
Reset
Table 13-37 shows the bit settings of the subsystem vendor ID configuration register.
Table 13-37. Subsystem Vendor ID Configuration Register Field Descriptions
Bits Name
15–0 SVID
13.3.3.18 Subsystem Device ID Configuration Register
Figure 13-36 shows the subsystem device configuration register ID fields. The subsystem device ID
configuration register is read-only from the PCI bus, but it can be programmed from the CSB.
Offset 0x2E
15
R
W
Reset
Table 13-38 shows the bit settings of the subsystem device ID configuration register.
Table 13-38. Subsystem Device ID Configuration Register Field Descriptions
Bits Name
15–0 SDID
13.3.3.19 Capabilities Pointer Configuration Register
The capabilities pointer register specifies the byte offset in the PCI configuration space that contains the
first item in the capabilities list.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-36
Figure 13-35. Subsystem Vendor ID Configuration Register
Subsystem vendor ID. Identifies the manufacturer of the board or subsystem that contains this
device.
Figure 13-36. Subsystem Device ID Configuration Register
Subsystem device ID. This field identifies the board or subsystem that contains this device.
Figure 13-37
SVID
All zeros
Description
SDID
All zeros
Description
shows the capabilities pointer configuration register fields.
Access: Read/Write
0
Access: Read/Write
0
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