Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 417

Table 9-14 describes the DDR_SDRAM_MODE fields.
Bits Name
0–15 ESDMODE Extended SDRAM mode. Specifies the initial value loaded into the DDR SDRAM extended mode register.
The range and meaning of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb of ESDMODE, which, in the big-endian convention shown in
ESDMODE[15]. The msb of the SDRAM extended mode register value must be stored at ESDMODE[0].
16–31 SDMODE SDRAM mode. Specifies the initial value loaded into the DDR SDRAM mode register. The range of legal
values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the lsb
of SDMODE, which, in the big-endian convention shown in
msb of the SDRAM mode register value must be stored at SDMODE[0]. Because the memory controller
forces SDMODE[7] to certain values depending on the state of the initialization sequence, the
corresponding bits of this field are ignored by the memory controller. Note that SDMODE[7] is mapped to
MA[8].
9.4.1.10 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)
The DDR SDRAM mode 2 configuration register, shown in
DDR's extended mode 2 and 3 registers (for DDR2).
Offset 0x11C
0
R
W
Reset
Figure 9-11. DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)
Table 9-15 describes the DDR_SDRAM_MODE_2 fields.
Bits Name
0–15 ESDMODE2 Extended SDRAM mode 2. Specifies the initial value loaded into the DDR SDRAM extended 2 mode
register. The range and meaning of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence),
MA[0] presents the lsb bit of ESDMODE2, which, in the big-endian convention shown in
corresponds to ESDMODE2[15]. The msb of the SDRAM extended mode 2 register value must be
stored at ESDMODE2[0].
16–31 ESDMODE3 Extended SDRAM mode 3. Specifies the initial value loaded into the DDR SDRAM extended 3 mode
register. The range of legal values of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of ESDMODE3, which, in the big-endian convention shown in
ESDMODE3[15]. The msb of the SDRAM extended mode 3 register value must be stored at
ESDMODE3[0].
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 9-14. DDR_SDRAM_MODE Field Descriptions
ESDMODE2
Table 9-15. DDR_SDRAM_MODE_2 Field Descriptions
Description
Figure 9-10, corresponds to SDMODE[15]. The
Figure 9-11, sets the values loaded into the
15 16
All zeros
Description
DDR Memory Controller
Figure 9-10, corresponds to
Access: Read/Write
ESDMODE3
Figure
Figure 9-11, corresponds to
31
9-11,
9-23