Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 106

Memory Map
In certain specific cases, reserved bits should not be cleared but should keep their reset value. Thus, the
software should perform a 'read-modify-write' and make sure that it does not change the reset value of
those bits. The description of the specific bits will indicate when this is needed.
Address
0x0_0000–0x0_01FF System configuration
0x0_0200–0x0_02FF Watchdog timer
0x0_0300–0x0_03FF Real time clock
0x0_0400–0x0_04FF Periodic interval timer
0x0_0500–0x0_05FF Global timers module 1
0x0_0600–0x0_06FF Global timers module 2
0x0_0700–0x0_07FF Integrated programable interrupt controller (IPIC)
0x0_0800–0x0_08FF System arbiter
0x0_0900–0x0_09FF Reset module
0x0_0A00–0x0_0AFF Clock module
0x0_0B00–0x0_0BFF Power management control module
0x0_0C00–0x0_0CFF GPIO
0x0_0D00–0x0_0DFF Reserved
0x0_0E00–0x0_0EFF Reserved
0x0_0F00–0x0_0FFF Reserved
0x0_1000–0x0_10FF Reserved
0x0_1100–0x0_11FF Reserved
0x0_1200–0x0_12FF Reserved
0x0_1300–0x0_13FF Reserved
0x0_1400–0x0_17FF Reserved
0x0_1800–0x0_1BFF Reserved
0x0_1C00–0x0_1FFF Reserved
0x0_2000–0x0_2FFF DDR MEMC
2
0x0_3000–0x0_30FF I
2
0x0_3100–0x0_31FF I
0x0_3200–0x0_32FF Reserved
0x0_3300–0x0_33FF Reserved
0x0_3400–0x0_37FF Reserved
0x0_3800–0x0_3BFF Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2-2
Table 2-1. IMMR Memory Map
Use
C1 controller
C2 controller
Actual Size Window
512 bytes 512 bytes
16 bytes 256 bytes
32 bytes 256 bytes
32 bytes 256 bytes
64 bytes 256 bytes
64 bytes 256 bytes
128 bytes 256 bytes
30 bytes 256 bytes
44 bytes 256 bytes
44 bytes 256 bytes
20 bytes 256 bytes
24 bytes 256 bytes
— 256 bytes
— 256 bytes
— 256 bytes
— 256 bytes
— 256 bytes
— 256 bytes
— 256 bytes
— 1 Kbyte
— 1 Kbyte
— 1 Kbyte
3.8 Kbytes 4 Kbytes
24 bytes 256 bytes
24 bytes 256 bytes
— 256 bytes
— 256 bytes
— 1 Kbyte
— 1 Kbyte
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