Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 441

9.5.8.2.1 Self-Refresh in Sleep Mode
The entry and exit timing for self-refreshing SDRAMs is shown in
SDRAM Clock
MCKE
MCS
MRAS
MCAS
MA n
MWE
MDQ n
MDQS
SDRAM Clock
MCKE
MCS
MRAS
MCAS
MA n
MWE
MDQ n
MDQS
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
0 1 2 3 4
(High Impedance)
Figure 9-32. DDR SDRAM Self-Refresh Entry Timing
0 1 2 3 4
(High Impedance)
Figure 9-33. DDR SDRAM Self-Refresh Exit Timing
Figure 9-32
5 6 7 8 9
5 6 7 202 203
200 Cycles
DDR Memory Controller
and Figure 9-33.
10 11 12
204 205 206
9-47