Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 227

whenever an internal unit requests mastership of the coherent system bus (CSB). The SPCR also includes
some other control functions.
Offset 0x00110
0
R
BUFGTX
BUFMDIO —
125
W
1
Reset n n
16 17
R
TSEC1588
W
Reset
1
Default values depend on CFG_RESET_SRC value. See
Table 5-26 defines the bit fields of SPCR.
'
Bits Name
0 BUFGTX125 0 A signal is supplied from an external PHY or oscillator to TSEC1_GTX_CLK125 has the same
1 A 2.5 V signal is supplied to TSEC1_GTX_CLK125 from an external PHY or oscillator, and the
1 BUFMDIO 0 A 3.3 V signal is supplied from external phy to TSEC1_MDIO.
1 A 2.5 V signal is supplied from external phy to TSEC1_MDIO.
2 — Reserved. Should be cleared.
3 PCIHPE PCI highest priority enable. If this bit is set, the PCI bridge is permitted to request the coherent system
bus (CSB) with highest priority, regardless of SPCR[PCIPR] value, when it needs to complete a posted
write transaction from an external PCI master. To follow PCI ordering rules specifications, the PCI
bridge must flush any outstanding write transactions before it can start a new read transaction. Setting
this bit allows faster flushing of the outstanding write transactions coming from the PCI bus onto the
CSB and to the device targets, such as DDR SDRAM and local bus memories.
4–5 — Reserved. Should be cleared.
6–7 PCIPR PCI bridge CSB request priority. The level of priority can be chosen from 4 possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
Note: DMA has the same priority as PCI.
8 OPT Optimize. Setting this bit may enhance the performance of transactions issued to the internal coherent
system bus (CSB) by the security engine (SEC) and the USB controller. Performance is enhanced by
reading more bytes on the bus than actually needed by the master in the case that this is more efficient.
The user may set this bit only if it is known that USB transactions sent to the internal CSB are not
accessing devices in which speculative reads may change the state of the device (for example, FIFOs
in which reading a byte may advance some internal counter).
0 No performance enhancement.
1 Performance enhancement by speculative reading is enabled.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2 3 4
PCIHPE
1
0 0 0
18 19 20
TSECDP TSECBDP
Figure 5-13. System Priority Configuration Register (SPCR)
Table 5-26. SPCR Bit Settings
voltage level as the LVddb power supply.
LVdbb power supply has a 3.3 V voltage level.
5 6 7 8
— PCIPR OPT
0 0 0 0
21 22 23 24
TSECEP
All zeros
Table 5-27.
Description
System Configuration
Access: Read/Write
9 10 11 12
TBEN COREPR
0 0 0 0
25 26 27 28
—
15
—
0 0 0
29 30 31
5-19