Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 747

Bits Name
10 TXBEN Transmit buffer interrupt enable
11 TXFEN Transmit frame interrupt enable
12 — Reserved
13 LCEN Late collision enable
14 CRLEN Collision retry limit enable
15 XFUNEN Transmit FIFO underrun enable
16 RXBEN Receive buffer interrupt enable
17–19 — Reserved
20 MAGEN Magic packet received interrupt enable
21 MMRDEN MII management read completion interrupt enable
22 MMWREN MII management write completion interrupt enable
23 GRSCEN Graceful receive stop complete interrupt enable
24 RXFEN Receive frame interrupt enable
25–26 — Reserved
27 FGPIEN Filer general purpose interrupt enable
28 FIREN Filer invalid result interrupt enable
29 FIQEN Filed frame to invalid queue interrupt enable
30 DPEEN Data parity error interrupt enable
31 PERREN Receive frame parse error enable
15.5.3.1.5 Error Disabled Register (EDIS)
Figure 15-6 describes the definition for the EDIS register. The error disabled register allows the user to
disable an error interruption, possibly to avoid spurious error indications external to the eTSECs.
Offset eTSEC1:0x2_4018; eTSEC2:0x2_5018
0 1 2
R
— BSYDIS EBERRDIS
W
Reset
16
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-9. IMASK Field Descriptions (continued)
3 4 6
— BABTDIS — TXEDIS
—
Figure 15-6. EDIS Register Definition
Enhanced Three-Speed Ethernet Controllers
Description
7 8 9 10
—
All zeros
27
All zeros
Access: Read/Write
12 13 14
LCDIS CRLDIS XFUNDIS
28 29 30
FIRDIS FIQDIS DPEDIS PERRDIS
15
31
15-29