Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 836

Enhanced Three-Speed Ethernet Controllers
Only one of this register is required for the entire group of eTSECs. Figure 15-110 describes the definition
of the TMR_ADD register.
Offset eTSEC1:0x2_4E20
0
R
W
Reset
Table 15-118 describes the fields of the TMR_ADD register fields for the timer.
Bits Name
0–31 ADDEND
15.5.3.10.9 Timer Accumulator Register (TMR_ACC)
Timer accumulator register accumulates the value of the addend register into it. An overflow pulse of the
accumulator is used to increment the timer clock by TMR_CTRL[TCLK_PERIOD]. This register is read
only in normal operation. The register in eTSEC1 is shared for all eTSECs. Figure 15-111 describes the
definition of the TMR_ACC register.
Offset eTSEC1:0x2_4E24
0
R
W
Reset
Table 15-119 describes the fields of the TMR_ACC register.
Bits Name
0–31 TMR_ACC
15.5.3.10.10 Timer Prescale Register (TMR_PRSC)
Timer generated output clock prescale register. It is used to adjust output clock frequency that is put onto
the 1588 clock output signal. The register in eTSEC1 is shared for all eTSECs. Figure 15-112 describes
the definition for the TMR_PRSC register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-118
Figure 15-110. TMR_ADD Register Definition
Table 15-118. TMR_ADD Register Field Descriptions
Timer drift compensation addend register value. It is programmed with a value of 2^32/FreqDivRatio.
For example,
TimerOsc = 50 MHz
NominalFreq = 40 MHz
FreqDivRatio = 1.25
ADDEND = ceil(2^32/1.25) = 0xCCCC_CCCD
Figure 15-111. TMR_ACC Register Definition
Table 15-119. TMR_ACC Register Field Descriptions
32-bit timer accumulator register
ADDEND
All zeros
Description
TMR_ACC
All zeros
Description
Access: Read/Write
31
Access: Read/Write
31
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