Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 850

Enhanced Three-Speed Ethernet Controllers
Table 15-134 describes the fields of the EXST register.
Bits Name
0 1000X Full
1 1000X Half
2 1000T Full
3 1000T Half
4–15 —
15.5.4.3.9 Jitter Diagnostics Register (JD)
Annex 36A in IEEE 802.3z describes several jitter test patterns. These can be configured to be sent by
writing the jitter diagnostics register. See the register description for more information. In may be wise to
auto-negotiate and advertise a remote fault signaling of offline prior to beginning the test patterns.
Figure 15-125 describes the definition for the JD register.
Offset 0x10
0
R Jitter
Enable
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-132
Table 15-134. EXST Field Descriptions
1000X full-duplex capability. Returns 1 on read. This bit is read-only.
0 PHY cannot operation in 1000BASE-X full-duplex mode.
1 PHY can operate in 1000BASE-X full-duplex mode.
1000X half-duplex capability. Returns 0 on read. This bit is read-only.
0 PHY cannot operation in 1000BASE-X half-duplex mode.
1 PHY can operate in 1000BASE-X half-duplex mode.
1000T full-duplex capability. Returns 1 on read. This bit is read-only.
0 PHY cannot operation in 1000BASE-T full-duplex mode.
1 PHY can operate in 1000BASE-T full-duplex mode.
1000T half-duplex capability. Returns 0 on read. This bit is read-only.
0 PHY cannot operation in 1000BASE-T half-duplex mode.
1 PHY can operate in 1000BASE-T half-duplex mode.
Reserved
1 3 4
Jitter Select —
Figure 15-125. Jitter Diagnostics Register Definition
Description
5 6
All zeros
Access: Read/Write
Custom Jitter Pattern
Freescale Semiconductor
15