Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 695

14.4.3.9.5 AESU Key Registers
The AESU key registers hold from 16, 24, or 32 bytes of key data, with the first 8 bytes of key data written
to key 1. Any key data written to bytes beyond the value written to the key size register will be ignored.
The key data registers are cleared when the AESU is reset or re-initialized. If these registers are modified
during message processing, a context error will be generated.
The key data registers may be read when changing context in decrypt mode. To resume processing, the
value read must be written back to the key registers and the 'restore decrypt key' bit must be set in the
mode register. This eliminates the overhead of expanding the key prior to starting decryption when
switching context.
14.4.3.9.6 AESU FIFOs
The AESU fetches data 128 bits at a time from the shared symmetric input FIFO. During processing, the
input data is encrypted or decrypted with the key and initialization vector (CBC mode only) and the results
are placed in the shared symmetric output FIFO. The output size is the same as the input size.
Writing to the AESU FIFO address space places 64 bits of message data into the input FIFO and configures
the shared symmetric FIFOs to be reserved by AESU. The input FIFO may be written any time the IFW
signal is asserted (as indicated in the AESU status register). This will indicate that the number of bytes of
available space is at or above the threshold specified in the mode register. There is no limit on the total
number of bytes in a message. The number of bits in the final message block must be set in the data size
register.
Reading from the AESU FIFO address space will pop 64 bits of message data from the shared symmetric
output FIFO. The output FIFO may be read any time the OFR signal is asserted (as indicated in the AESU
status register). This will indicate that the number of bytes in the output FIFO is at or above the threshold
specified in the mode register.
14.5 Channel
The channel in the SEC manages the execution of each cryptographic task, making use of one or more of
the SEC's execution units (EUs). Control information and data pointers for a given task are stored in the
form of a descriptor (see
A descriptor determines what EUs will be used, how they will be configured, where to fetch needed data,
and where to store the results. To invoke cryptographic tasks, the host constructs a descriptor, and writes
a pointer to the descriptor into the channel's fetch FIFO. The fetch FIFO can store up to 24 pointers.
Operations performed by the channel include the following (not necessarily in this order):
• If the channel is idle and its fetch FIFO is non-empty, read the next descriptor pointer from the fetch
FIFO, and use this pointer to read the descriptor into the channel's descriptor buffer.
• Request from the controller the assignment of one or more EUs for the use of the channel. Where
necessary, configure the secondary EU to snoop input or output data intended for the primary EU.
• Upon notification of completion of the EU reset sequence, initialize mode registers in the assigned
EU.
• Initialize EUs and write to EU registers such as key size and text-data size.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Section 14.3.1, "Descriptor Structure") in system memory or in the channel itself.
Security Engine (SEC) 2.2
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