Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 286

System Configuration
Table 5-74. Software-Controller Power-Down States—Basic Description (continued)
System Core Suggested
Mode Mode PCI D- state
Low Power Nap
(PMCCR[SL PCIPMR1[P
PEN]=1) owerState]=
Sleep
PCIPMR1[P
owerState]=
Lowest Power D3Warm
Power Off, PCIPMR1[P
(PMCCR[SL Deep owerState]=
PEN]=1), Sleep
PMCCR1[P
OWER_OFF
] = 1
5.8.3.5.1 Entering Low Power States—Core-Only Mode
Entering Doze mode is controlled only by the e300 PowerPC core itself, and does not involve the power
management controller or other blocks. For a more detailed description, see
Entering Nap or Sleep modes occurs by writing to HID0 in the core, causing the core to make a quiesce
request to the power management controller while PMCCR[SLPEN] is cleared. The core is immediately
enabled to enter low power state, regardless of the system status. Note that since the core does not snoop
the bus in this mode, it is the user's responsibility to keep the cache coherent. Other device peripheral and
internal units continue to operate in full-on mode while the core is in low power state in this mode.
5.8.3.5.2 Entering Low Power States—Core and System Mode
Core and system mode is achieved when the core makes a quiesce request to the power management
controller after PMCCR[SLPEN] is set. To preserve cache coherency and otherwise avoid loss of system
state, the core's transition to low-power modes is coordinated with other functional blocks. The power
management controller allows the core to enter power down mode only when the rest of the system is idle.
When the power management controller detects that the internal system bus is idle, and there are no
outstanding transactions, it signals the internal logic units to enter low power state.
If PMCCR[DLPEN] is set, the DDR SDRAM is first set to self-refresh mode (if enabled by
DDR_SDRAM_CFG[SREN] memory controller register) before the memory controller stops driving
refresh commands. Self-refresh mode guarantees that the memory content will remain valid while the
memory controller and its clocks are off. The DDR clocks are then disabled. Finally the DDR SDRAM
memory controller enters low power state and acknowledges the power management controller.
The power management controller then signals the core and acknowledges it's request to enter power
down mode. Finally the QUIESCE output signal is asserted.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-78
Description
D3 Core operation as described above. System
is in idle state, DDR SDRAM memory
operates in self-refresh mode if
11 enabled.
D3 Core operation as described above. System
is in idle state, DDR SDRAM memory
operates in self-refresh mode if
11 enabled.
This state is an extension of the above low
power modes where power can be removed
to a portion of the device die using an
11 external power switch. Software enters core
"Sleep" mode with
PMCCR1[POWER_OFF] = 1. Wake-up is in
response to defined Wake-up events.
Core Responds
DDR
to
SDRAM
strl state
Snoop Interrupt
No Yes According
to
PMCCR[D
LPEN]
No Yes According
to
PMCCR[D
LPEN]
No No PMCCR[D
LPEN] = 1
Table 7-1.
Freescale Semiconductor
Quiesce
Signal
State
Asserted
Asserted
Asserted