Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 468

Enhanced Local Bus Controller
10.3.1.4 UPM Mode Registers (M
The UPM machine mode registers (MAMR, MBMR and MCMR), shown in
configuration for the three UPMs.
Offset MAMR: 0x0_5070
MBMR: 0x0_5074
MCMR: 0x0_5078
0 1 2
R
— RFEN
W
Reset
16 17 18
R
RLF
W
Reset
Table 10-11 describes UPM mode fields.
Bits Name
0 — Reserved
1 RFEN Refresh enable. Indicates that the UPM needs refresh services. This bit must be set for UPMA (refresh
executor) if refresh services are required on any UPM assigned chip selects. If MAMR[RFEN] = 0, no refresh
services can be provided, even if UPMB and/or UPMC have their RFEN bit set.
0 Refresh services are not required
1 Refresh services are required
Command opcode. Determines the command executed by the UPM n when a memory access hits a UPM
2–3 OP
assigned bank.
00 Normal operation
01 Write to UPM array. On the next memory access that hits a UPM assigned bank, write the contents of the
MDR into the RAM location pointed to by MAD. After the access, MAD is automatically incremented.
10 Read from UPM array. On the next memory access that hits a UPM assigned bank, read the contents of
the RAM location pointed to by MAD into the MDR. After the access, MAD is automatically incremented.
11 Run pattern. On the next memory access that hits a UPM assigned bank, run the pattern written in the
RAM array. The pattern run starts at the location pointed to by MAD and continues until the LAST bit is
set in the RAM word.
4 UWPL LUPWAIT polarity active low. Sets the polarity of the LUPWAIT pin when in UPM mode.
0 LUPWAIT is active high.
1 LUPWAIT is active low.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-20
x
3 4 5
OP UWPL AM
21
WLF
Figure 10-7. UPM Mode Registers (M
Table 10-11. M
MR)
7 8 9
DS
All zeros
22 25
TLF
All zeros
MR Field Descriptions
x
Description
Figure 10-7, contain the
Access: Read/Write
10 12 13
G0CL GPL4
26
MAD
MR)
x
Freescale Semiconductor
14 15
RLF
31