Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 502

Enhanced Local Bus Controller
10.4.2.3.4 Output Enable (LOE) Timing
The timing of the LOE is affected only by TRLX. It always asserts and negates on the rising edge of the
bus clock. LOE asserts either on the rising edge of the bus clock after LCSn is asserted or coinciding with
LCSn (if XACS = 1 and ACS = 10 or ACS = 11). Accordingly, assertion of LOE can be delayed (along
with the assertion of LCSn) by programming TRLX = 1. LOE negates on the rising clock edge coinciding
with LCSn negation
10.4.2.3.5 Extended Hold Time on Read Accesses
Slow memory devices that take a long time to disable their data bus drivers on read accesses should choose
some combination of ORn[TRLX,EHTR]. Any access following a read access to the slower memory bank
is delayed by the number of clock cycles specified in
cycle. The final bus turnaround cycle is automatically inserted by the eLBC for reads, regardless of the
setting of OR [EHTR].
n
LCLK
LAD
Address 1
LALE
A
TA
LCS n
LCSy
LBCTL
LOE
Figure 10-41. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-54
Table 10-7
Read Data 1
Bus turnaround
Latched Address 1
in addition to any existing bus turnaround
Address 2
Latched Address 2
Freescale Semiconductor
Data 2