Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 619

Offset 0x34
7
R
W
Reset 0
13.3.3.20 Interrupt Line Configuration Register
Figure 13-38 shows the interrupt line configuration register fields.
Offset 0x3C
7
R
W
Reset
Table 13-39 shows the bit settings of the interrupt line configuration register.
Table 13-39. Interrupt Line Configuration Register Field Descriptions
Bits Name
7–0 IL
13.3.3.21 Interrupt Pin Configuration Register
The interrupt pin configuration register tells which interrupt pin is used (0x01 means PCI_INTA).
Figure 13-39 shows the interrupt pin configuration register fields.
Offset 0x3D
7
R
W
Reset 0
13.3.3.22 Minimum Grant Configuration Register
Figure 13-40 shows the minimum grant configuration register fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
1 0
Figure 13-37. Capabilities Pointer Configuration Register
Figure 13-38. Interrupt Line Configuration Register
Interrupt line. Used to communicate interrupt line routing information. The value has no effect on the
operation of the PCI controller.
0 0
Figure 13-39. Interrupt Pin Register
Capabilities Pointer
0 1
IL
All zeros
Description
Interrupt Pin
0 0
PCI Bus Interface
Access: Read-only
0 1
Access: Read/Write
0 0
0
0
0
0
1
13-37