Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 794

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.11 MII Management Indicator Register (MIIMIND)
The MIIMIND register is read-only by the user.
register.
Offset eTSEC1:0x2_4534
0
R
W
Reset
Bits Name
0–28 —
29 Not Valid Not valid.
30 Scan
31 Busy
15.5.3.5.12 Interface Status Register (IFSTAT)
Figure 15-47 shows the IFSTAT register.
Offset eTSEC1:0x2_453C; eTSEC2:0x2_553C
0
R
W
Reset
Table 15-51 describes the fields of the FSTAT register.
Bits Name
0–21 — Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-76
—
Figure 15-46. MII Mgmt Indicator Register Definition
Table 15-50. MIIMIND Field Descriptions
Reserved
0 MII Mgmt read cycle has completed and the read data is valid.
1 MII Mgmt read cycle has not completed and the read data is not yet valid.
Scan in progress.
0 A scan operation (continuous MII Mgmt read cycles) is not in progress.
1 A scan operation (continuous MII Mgmt read cycles) is in progress.
Busy.
0 MII Mgmt block is not currently performing an MII Mgmt read or write cycle.
1 MII Mgmt block is currently performing an MII Mgmt read or write cycle.
—
Figure 15-47. Interface Status Register Definition
Table 15-51. IFSTAT Field Descriptions
Figure 15-46 describes the definition for the MIIMIND
All zeros
Description
21
Excess Defer
All zeros
Description
Access: Read only
28 29 30
Not Valid Scan
Access: Read only
22 23
—
Freescale Semiconductor
31
Busy
31