Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 193

Table 4-24. Hard-Coded Reset Configuration Word High Field Values
Bits Name
0 PCIHOST
1 Reserved
2 PCIARB
3 Reserved
4 COREDIS
5 BMS
6–7 BOOTSEQ
8 SWEN
9–11 ROMLOC
12–13 RLEXT
14–15 Reserved
16–18 TSEC1M
19–21 TSEC2M
22–27 Reserved
28 TLE
29 LALE
30–31 Reserved
4.3.3.3.1 Examples for Hard-Coded Reset Configuration Words Usage
Examples for various clock modes are listed in
Table 4-25. Examples For Hard-Coded Reset Configuration Words Usage
CFG_RESET_SOURCE[0:3]
PCI_CLK (MHz)
csb_clk (MHz)
DDR controller clock (MHz)
Core clock (MHz)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Field Values when
CFG_RESET_SOURCE[0:3] = 1000–1100
1000 1001 1010
0
1
0
0
1
1
00
0
000
00
00
101 011 000
000 101 001
000000
0
0
00
1000
33
133
266
266
1100
PCI agent mode
External arbiter is used
e300 core is disabled (boot holdoff)
Boot memory space is 0xFF80_0000–
0xFFFF_FFFF. MSR[IP] initial value is 0b1.
Boot sequencer is disabled.
Software watchdog disabled.
Boot ROM interface location.
Legacy mode.
001 000 = MII mode
001 = RMII
101
011 = RGMII mode
101 = RTBI mode
Big-endian mode
Normal timing
Table 4-25.
1001 1010
66 33
133 167
266 333
333 250
Reset, Clocking, and Initialization
Meaning
—
—
—
—
—
1011 1100
66 33
133 167
266 333
266 333
4-27