Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 402

DDR Memory Controller
Table 9-4. Clock Signals—Detailed Signal Descriptions (continued)
Signal I/O
MCKE O Clock enable. Output signals used as the clock enables to the SDRAM. MCKE can be negated to stop
clocking the DDR SDRAM. The MCKE signals should be connected to the same rank of memory as the
corresponding MCS and MODT signals. For example, MCKE[0] should be connected to the same rank of
memory as MCS[0] and MODT[0].
State
Meaning
Timing Assertion/Negation—Asserted when DDR_SDRAM_CFG[MEM_EN] is set. Can be negated
9.3.2.3 Debug Signals
The debug signals MSRCID[0:4] and MDVAL have no function in normal DDR controller operation. A
detailed description of these signals can be found in
9.4 Memory Map/Register Definition
Table 9-5 shows the register memory map for the DDR memory controller.
In this table and in the register figures and field descriptions, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
• Mixed indicates a combination of access types.
• Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Offset
0x000 CS0_BNDS—Chip select 0 memory bounds
0x008 CS1_BNDS—Chip select 1 memory bounds
0x080 CS0_CONFIG—Chip select 0 configuration
0x084 CS1_CONFIG—Chip select 1 configuration
0x100 TIMING_CFG_3—DDR SDRAM timing configuration 3
0x104 TIMING_CFG_0—DDR SDRAM timing configuration 0
0x108 TIMING_CFG_1—DDR SDRAM timing configuration 1
0x10C TIMING_CFG_2—DDR SDRAM timing configuration 2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-8
Asserted—Clocking to the SDRAM is enabled.
Negated—Clocking to the SDRAM is disabled and the SDRAM should ignore signal transitions
on MCK or MCK. MCK/MCK are don't cares while MCKE is negated.
when entering dynamic power management or self refresh. Are asserted again when
exiting dynamic power management or self refresh.
High impedance—Always driven.
Table 9-5. DDR Memory Controller Memory Map
Register
DDR Memory Controller—Block Base Address 0x0_2000
Description
Section 5.4.3.8, "Debug
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Configuration."
Reset Section/Page
0x0000_0000 9.4.1.1/9-9
0x0000_0000 9.4.1.1/9-9
0x0000_0000 9.4.1.2/9-10
0x0000_0000 9.4.1.2/9-10
0x0000_0000 9.4.1.3/9-11
0x0011_0105 9.4.1.4/9-12
0x0000_0000 9.4.1.5/9-14
0x0000_0000 9.4.1.6/9-16
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