Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 854

Enhanced Three-Speed Ethernet Controllers
eTSEC
2
The management signals (MDC and MDIO) are common to all of the Ethernet controllers module
connections in the system, assuming that each PHY has a different management address.
15.6.1.3 Reduced Gigabit Media-Independent Interface (RGMII)
This section describes the reduced gigabit media-independent interface (RGMII) intended to be used
between the PHYs and the GMII MAC. The RGMII is an alternative to the IEEE802.3u MII, the
IEEE802.3z GMII. The RGMII reduces the number of signals required to interconnect the MAC and the
PHY from a maximum of 28 signals (GMII) to 15 signals (GTX_CLK125 included) in a cost effective and
technology independent manner. To accomplish this objective, the data paths and all associated control
signals are multiplexed using both edges of the clock. For gigabit operation, the clocks operate at 125MHz,
and for 10/100 operation, the clocks operate at 2.5 MHz or 25 MHz, respectively. Note that the
GTX_CLK125 input must be provided at 125 MHz for an RGMII interface, regardless of operation speed
(1 Gbps, 100 Mbps, or 10 Mbps).
media-independent interface and the signals required to establish the gigabit Ethernet controllers' module
connection with a PHY. The RGMII is implemented as defined by the RGMII specification Version 1.2a
9/22/00.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-136
Reference Clock (TSEC n _TX_CLK)
Transmit Control (TX_EN)
Transmit Data (TSEC n _TXD[1:0])
Receive Control (RX_DV, RX_ER)
Receive Data (TSEC n _RXD[1:0])
Management Data Clock
Management Data I/O
Figure 15-128. eTSEC-RMII Connection
Figure 15-129 depicts the basic components of the gigabit reduced
2
(MDC)
2
(MDIO)
RMII
Ethernet
PHY
Medium
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