Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 18

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Number
12.3.7 Inbound Message Interrupt Mask Register (IMIMR)................................................ 12-8
12.3.8 DMA Registers .......................................................................................................... 12-9
12.3.8.1 DMA Mode Register (DMAMRn) ........................................................................ 12-9
12.3.8.2 DMA Status Register (DMASRn) ....................................................................... 12-11
12.3.8.3 DMA Current Descriptor Address Register (DMACDARn) .............................. 12-12
12.3.8.4 DMA Source Address Register (DMASARn)..................................................... 12-13
12.3.8.5 DMA Destination Address Register (DMADARn)............................................. 12-13
12.3.8.6 DMA Byte Count Register (DMABCRn) ........................................................... 12-14
12.3.8.7 DMA Next Descriptor Address Register (DMANDARn)................................... 12-14
12.3.8.8 DMA General Status Register (DMAGSR)......................................................... 12-15
12.4 Functional Description................................................................................................. 12-15
12.4.1 Message Unit ........................................................................................................... 12-15
12.4.1.1 Messaging Registers (IMR0–IMR1, OMR0–OMR1) ......................................... 12-15
12.4.1.2 Doorbell Registers (IDR and ODR) .................................................................... 12-16
12.4.2 DMA Controller....................................................................................................... 12-16
12.4.3 DMA Operation ....................................................................................................... 12-16
12.4.3.1 DMA Coherency.................................................................................................. 12-17
12.4.3.2 Halt and Error Conditions.................................................................................... 12-17
12.4.4 DMA Segment Descriptors...................................................................................... 12-18
12.4.4.1 Descriptor in Big-Endian Mode........................................................................... 12-19
12.4.4.2 Descriptor in Little-Endian Mode........................................................................ 12-20
12.5 Initialization/Application Information ......................................................................... 12-20
12.5.1 Initialization Steps in Direct Mode.......................................................................... 12-20
12.5.2 Initialization Steps in Chaining Mode ..................................................................... 12-20
13.1 Introduction.................................................................................................................... 13-1
13.1.1 Features...................................................................................................................... 13-3
13.1.2 Modes of Operation ................................................................................................... 13-3
13.1.2.1 Host/Agent Mode Configuration ........................................................................... 13-3
13.1.2.2 PCI Arbiter Configuration ..................................................................................... 13-4
13.2 External Signal Description ........................................................................................... 13-4
13.3 Memory Map/Register Definitions .............................................................................. 13-11
13.3.1 PCI Configuration Access Registers........................................................................ 13-12
13.3.1.1 PCI_CONFIG_ADDRESS .................................................................................. 13-13
13.3.1.2 PCI_CONFIG_DATA.......................................................................................... 13-14
13.3.1.3 PCI Interrupt Acknowledge Register (PCI_INT_ACK)...................................... 13-15
13.3.2 PCI Memory-Mapped Control and Status Registers ............................................... 13-15
13.3.2.1 PCI Error Status Register (PCI_ESR) ................................................................. 13-15
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
xviii
Contents
Title
Chapter 13
PCI Bus Interface
Page
Number
Freescale Semiconductor