Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 278

System Configuration
5.8.2.3 Power Management Controller Mask Register (PMCMR)
The power management controller mask register (PMCMR), shown in
PMCIE bit whether the PMC interrupt request to the PowerPC core is enabled. The PMC interrupt request
causes the PowerPC core to exit its low power state before any transaction on the system bus occurs. Bits
23–30 are mask bits for the defined low power wake-up events.
Offset 0x00B08
0
R
W
Reset
16
R
—
W
Reset
Table 5-69 defines the bit fields of PMCMR.
Bits Name
0–22 —
23–30 GPIO, PCI(PME),
USB, eTSEC1,
eTSEC2, Timer,
Int1, Int2
31 PMCIE
The user is also required to enable the PMC interrupt in the programmable
interrupt controller by setting SIMSR_L[PMC].
5.8.2.4 Power Management Controller Configuration Register 1 (PMCCR1)
The power management controller configuration register 1 (PMCCR1), shown in
sequencing of the device into its low power state including PME (power management event) signaling,
toggling of the external power switch, and indication of current and desired power states.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-70
22 23 24
GPIO PCI (PME)
Figure 5-53. Power Management Controller Mask Register
Table 5-69. PMCMR Bit Settings
Reserved. Write has no effect, read returns 0.
Wake-up event masking.
0 Mask wake-up events from Int2, Int1, Timer, eTSEC2, eTSEC1, USB, PCI, or GPIO,
respectively.
1 Do not mask wake-up events
Power management controller interrupt enable.
0 PMC interrupt request (PMCI) is disabled.
1 PMC interrupt request (PMCI) is enabled.
Figure
—
All zeros
25 26
USB eTSEC1 eTSEC2 Timer
All zeros
Description
NOTE
5-53, controls through the
Access: Read/Write
27 28 29 30
Int1 Int2
Figure 5-54, controls the
Freescale Semiconductor
15
31
PMCIE