Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 466

Enhanced Local Bus Controller
Bits Name
30 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
access from the current bank and the next access.
TRLX
31 — Reserved
10.3.1.2.4 Option Registers (OR
Figure 10-5 shows the bit fields for ORn when the corresponding BRn[MSEL] selects a UPM machine.
Offset OR0: 0x0_5004
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
0
R
W
Reset
16 17 18
R
AM —
W
Reset
1
Refer to Table 10-5 for the OR0 reset value. All other option registers have all bits cleared.
Table 10-9 describes BR
Bits Name
0–16 AM UPM address mask. Masks corresponding BR n bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked.
1 The corresponding address bits are used in the comparison with address pins.
17–18 — Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-18
—
Table 10-8. OR FCM Field Descriptions (continued)
n
EHTR
0 0 1 idle clock cycle is inserted.
0 1 2 idle clock cycles are inserted.
1 0 4 idle clock cycles are inserted.
1 1 8 idle clock cycles are inserted.
)—UPM Mode
n
19 20 22
BCTLD —
Figure 10-5. Option Registers (OR
fields for UPM mode.
n
Table 10-9. OR
Description
Meaning
AM
All zeros
23 24
BI —
1
All zeros
) in UPM Mode
n
—
UPM Field Descriptions
n
Description
Access: Read/Write
28 29 30
TRLX EHTR EAD
Freescale Semiconductor
15
31