Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 19

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13.3.2.2 PCI Error Capture Disable Register (PCI_ECDR).............................................. 13-16
13.3.2.3 PCI Error Enable Register (PCI_EER)................................................................ 13-17
13.3.2.4 PCI Error Attributes Capture Register (PCI_EATCR) ........................................ 13-18
13.3.2.5 PCI Error Address Capture Register (PCI_EACR) ............................................. 13-19
13.3.2.6 PCI Error Extended Address Capture Register (PCI_EEACR) .......................... 13-20
13.3.2.7 PCI Error Data Low Capture Register (PCI_EDLCR)........................................ 13-20
13.3.2.8 PCI General Control Register (PCI_GCR).......................................................... 13-20
13.3.2.9 PCI Error Control Register (PCI_ECR) .............................................................. 13-21
13.3.2.10 PCI General Status Register (PCI_GSR)............................................................. 13-22
13.3.2.11 PCI Inbound Translation Address Registers (PITARn)....................................... 13-22
13.3.2.12 PCI Inbound Base Address Registers (PIBARn)................................................. 13-23
13.3.2.13 PCI Inbound Extended Base Address Registers (PIEBARn) .............................. 13-24
13.3.2.14 PCI Inbound Window Attribute Registers (PIWARn)......................................... 13-24
13.3.3 PCI Configuration Space Registers ......................................................................... 13-25
13.3.3.1 Vendor ID Configuration Register....................................................................... 13-27
13.3.3.2 Device ID Configuration Register ....................................................................... 13-27
13.3.3.3 PCI Command Configuration Register................................................................ 13-28
13.3.3.4 PCI Status Configuration Register....................................................................... 13-29
13.3.3.5 Revision ID Configuration Register .................................................................... 13-30
13.3.3.6 Standard Programming Interface Configuration Register ................................... 13-30
13.3.3.7 Subclass Code Configuration Register ................................................................ 13-31
13.3.3.8 Base Class Code Configuration Register............................................................. 13-31
13.3.3.9 Cache Line Size Configuration Register ............................................................. 13-32
13.3.3.10 Latency Timer Configuration Register ................................................................ 13-32
13.3.3.11 Header Type Configuration Register ................................................................... 13-33
13.3.3.12 BIST Control Configuration Register.................................................................. 13-33
13.3.3.13 PIMMR Base Address Configuration Register ................................................... 13-33
13.3.3.14 GPL Base Address Register 0.............................................................................. 13-34
13.3.3.15 GPL Base Address Registers 1–2 ........................................................................ 13-34
13.3.3.16 GPL Extended Base Address Registers 1–2 ........................................................ 13-35
13.3.3.17 Subsystem Vendor ID Configuration Register .................................................... 13-36
13.3.3.18 Subsystem Device ID Configuration Register..................................................... 13-36
13.3.3.19 Capabilities Pointer Configuration Register........................................................ 13-36
13.3.3.20 Interrupt Line Configuration Register ................................................................. 13-37
13.3.3.21 Interrupt Pin Configuration Register ................................................................... 13-37
13.3.3.22 Minimum Grant Configuration Register ............................................................. 13-37
13.3.3.23 Maximum Latency Configuration Register ......................................................... 13-38
13.3.3.24 PCI Function Configuration Register .................................................................. 13-38
13.3.3.25 PCI Arbiter Control Register (PCIACR) ............................................................. 13-39
13.3.3.26 Hot Swap Register Block..................................................................................... 13-40
13.3.3.27 PCI Power Management Register 0 (PCIPMR0) ................................................ 13-41
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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