Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 846

Enhanced Three-Speed Ethernet Controllers
Local Device
PAUSE ASM_DIR
1 1
1 1
15.5.4.3.4 AN Link Partner Base Page Ability Register (ANLPBPA)
Figure 15-120 describes the definition for the ANLPBPA register.
Offset 0x05
0 1
R Next Page
—
W
Reset
Figure 15-120. AN Link Partner Base Page Ability Register Definition
Table 15-130 describes the fields of the ANLPBPA register.
Bits Name
0 Next Page Next page. This bit is read-only. The link partner sets or clears this bit.
0 Link partner has no subsequent next pages or is not capable of receiving next pages.
1 Link partner either requesting next page transmission or indicating the capability to receive next pages.
1 — Reserved. (Ignore on read)
2–3 Remote The link partner's remote fault condition is encoded in bits 2 and 3 of the base page. Values are shown in
Fault the remote fault encoding field table below. This bit is read-only.
4–6 — Reserved, should be cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-128
Table 15-129. PAUSE Priority Resolution (continued)
Link Partner
PAUSE ASM_DIR
0 1
1 x
2 3 4 6
Remote Fault
—
Table 15-130. ANLPBPA Field Descriptions
RF1 bit[3] RF2 bit[2]
0 0
0 1
1 0
1 1
Local Resolution
Disable PAUSE transmit
Enable PAUSE receive
Enable PAUSE transmit
Enable PAUSE receive
7 8 9
Pause Half Duplex Full Duplex
All zeros
Description
Description
No error, link OK
Offline
Link_Failure
Auto-Negotiation_Error
Link Partner Resolution
Enable PAUSE transmit
Disable PAUSE receive
Enable PAUSE transmit
Enable PAUSE receive
Access: Read/Write
10 11
—
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