Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 423

9.4.1.17 DDR IP Block Revision 2 (DDR_IP_REV2)
The DDR IP block revision 2 register, shown in
integration and configuration options.
Offset 0xBFC
0
R
—
W
Reset 0 0 0 0 0
Table 9-23 describes the DDR_IP_REV2 fields.
Bits Name
0–7 — Reserved
8–15 IP_INT IP block integration options
16–23 — Reserved
24–31 IP_CFG IP block configuration options
9.5 Functional Description
The DDR SDRAM controller controls processor and I/O interactions with system memory. It provides
support for JEDEC-compliant DDR2 and DDR SDRAMs. The memory system allows a wide range of
memory devices to be mapped to any arbitrary chip select, and support is provided for registered DRAM
modules and unbuffered DRAM modules. However, registered DRAM modules cannot be mixed with
unbuffered DRAM modules.
Figure 9-19 is a high-level block diagram of the DDR memory controller. Requests are received from the
internal mastering device and the address is decoded to generate the physical bank, logical bank, row, and
column addresses. The transaction is compared with values in the row open table to determine if the
address maps to an open page. If the transaction does not map to an open page, an active command is
issued.
The memory interface supports as many as two physical banks of 32-bit wide memory. Bank sizes up to
512 Mbytes are supported, providing up to a maximum of 512 Mbytes of DDR main memory.
Programmable parameters allow for a variety of memory organizations and timings. The controller allows
as many as 16 pages to be open simultaneously. The amount of time (in clock cycles) the pages remain
open is programmable with DDR_SDRAM_INTERVAL[BSTOPRE].
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
7 8
IP_INT
n n n n n n n n 0 0 0 0 0 0 0 0 n n n n n n n n
0 0 0
Figure 9-18. DDR IP Block Revision 2 (DDR_IP_REV2)
Table 9-23. DDR_IP_REV2 Field Descriptions
Figure 9-18, provides read-only fields with the IP block
15 16
—
Description
DDR Memory Controller
Access: Read Only
23 24 31
IP_CFG
9-29