Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 247

Table 5-40 defines the bit fields of RTCNR.
Bits Name
0–23 — Write reserved, read = 0
24 CLEN Clock enable control bit.
This bit controls the counting of the RTC. When the RTC's clock is disabled, the counter maintains its old
value. When the counter's clock is enabled, it continues counting using the previous value.
0 Disable counter.
1 Enable counter.
25 CLIN Input clock control bit.
The input clock to the RTC may be either the CSB clock or an external RTC clock.
0 The input clock to the periodic interrupt timer is CSB input clock.
1 The input clock to the periodic interrupt timer is the external RTC clock.
26–29 — Write reserved, read = 0
30 AIM Alarm interrupt mask bit.
Used to enable or disable (mask) the RTC alarm interrupt when the RTC's 32-bit counter reaches
RTALR[ALR] value.
0 Alarm interrupt generation disabled.
1 Alarm interrupt generation enabled.
31 SIM Second interrupt mask bit.
Used to enable or disable (mask) the RTC periodic interrupt.
0 Periodic interrupt generation disabled.
1 Periodic interrupt generation enabled.
5.5.5.2 Real Time Counter Load Register (RTLDR)
The real time counter load register (RTLDR), shown in
in the 32-bit RTC counter.
Offset 0x04
0
R
W
Reset
Table 5-41 defines the bit fields of RTLDR.
Bits Name
0–31 CLDV Contains the 32-bit value to be loaded in the 32-bit RTC counter.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 5-40. RTCNR Bit Settings
Figure 5-26. Real Time Counter Load Register (RTLDR)
Table 5-41. RTLDR Bit Settings
Description
Figure 5-26, contains the 32-bit value to be loaded
CLDV
All zeros
Description
System Configuration
Access: Read/Write
31
5-39