Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 827

15.5.3.9 Lossless Flow Control Configuration Registers
When enabled through RCTRL[LFC], the eTSEC tracks location of the last free BD in each Rx BD ring
through the value of RFBPTRn. Using this pointer and the ring length stored in RQPRMn[LEN], the
eTSEC continuously calculates the number of free BDs in the ring. Whenever the calculated number of
free BDs in the ring drops below the pause threshold specified in RQPRMn[FBTHR], the eTSEC issues
link layer flow control. It continues to assert flow control until the free BD count for each active ring
reaches or exceeds RQPRMn[FBTHR]. See section
registers.
15.5.3.9.1 Receive Queue Parameters 0–7 (RQPRM0–PQPRM7)
The RQPRMn registers specify the minimum number of BDs required to prevent flow control being
asserted and the total number of Rx BDs in their respective ring. Whenever the free BD count calculated
by the eTSEC for any active ring drops below the value of RQPRMn[FBTHR] for that ring, link level flow
control is asserted. Software must not write to RQPRMn while LFC is enabled and the eTSEC is actively
receiving frames. However, software may modify these registers after disabling LFC by clearing
RCTRL[LFC]. Note that packets may be lost due to lack of RxBDs while RCTRL[LFC] is clear. Software
can prevent packet loss by manually generating pause frames (through TCTRL[TFC_PAUSE]) to cover
the time when RCTRL[LFC] is clear.
Offset eTSEC1:0x2_4C00+4× n ; eTSEC2:0x2_5C00+4× n
0
R
FBTHR
W
Reset
Table 15-107 describes the fields of the RQPRM register.
Bits Name
0–7 FBTHR Free BD threshold. Minimum number of BDs required for normal operation. If the eTSEC calculated
number of free BDs drops below this threshold, link layer flow control is asserted.
8–31 LEN Ring length. Total number of Rx BDs in this ring.
15.5.3.9.2 Receive Free Buffer Descriptor Pointer Registers 0–7
(RFBPTR0–RFBPTR7)
The RFBPTRn registers specify the location of the last free buffer descriptor in their respective ring. These
registers live in the same 32b address space – and must share the same 4 most significant bits – as RBPTRn.
That is, RFBPTRn and its associated RBPTRn must remain in the same 256MB page. Like RBPTRn,
whenever RBASEn is updated, RFBPTRn is initialized to the value of RBASEn. This indicates that the
ring is completely empty. As buffers are freed and their respective BDs are returned (by setting the EMPTY
bit) to the ring, software is expected to update this register. The eTSEC then performs modulo arithmetic
involving RBASEn, RBPTRn and RFBPTRn to determine the number of free BDs remaining in the ring.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
15.6.5.1/15-175
Figure 15-103 describes the definition for the RQPRMn register.
7 8
Figure 15-103. RQPRM Register Definition
Table 15-107. RQPRM Field Descriptions
Enhanced Three-Speed Ethernet Controllers
for the theory of operation of these
LEN
All zeros
Description
Access: Read/Write
31
15-109