Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 527

10.4.4.4.1 RAM Words
The RAM word is a 32-bit microinstruction stored in one of 64 locations in the RAM array. It specifies
timing for external signals controlled by the UPM.
LCRR[CLKDIV] = 4 or 8, the CST
LBS[0:1] at each quarter phase of the bus clock. When LCRR[CLKDIV] = 2, CST2 and CST4 are ignored
and the external has the values defined by CST1 and CST3 but extended to half the clock cycle in duration.
The same interpretation occurs for the BST
0 1 2
R
CST1 CST2 CST3 CST4 BST1 BST2 BST3 BST4
W
Reset
16 17 18
R
G4T1/
G3T1 G3T3
DLT3
W
Reset
Table 10-40 contains descriptions of the RAM word fields.
Bits Name
0 CST1
1 CST2
2 CST3
3 CST4
4 BST1
5 BST2
6 BST3
7 BST4
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
and BST
n
bits when LCRR[CLKDIV] = 2.
n
3 4 5
19 20 21 22
G4T3/
G5T1 G5T3
WAEN
Figure 10-64. RAM Word Fields
Table 10-40. RAM Word Field Descriptions
Chip select timing 1. Defines the state (0 or 1) of LCS n during bus clock quarter phase 1 if
LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCS n during bus clock half phase 1 if
LCRR[CLKDIV] = 2.
Chip select timing 2. Defines the state (0 or 1) of LCS n during bus clock quarter phase 2 if
LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.
Chip select timing 3. Defines the state (0 or 1) of LCS n during bus clock quarter phase 3 if
LCRR[CLKDIV] = 4 or 8. Defines the state (0 or 1) of LCS n during bus clock half phase 2 if
LCRR[CLKDIV] = 2.
Chip select timing 4. Defines the state (0 or 1) of LCS n during bus clock quarter phase 4 if
LCRR[CLKDIV] = 4 or 8. Ignored when LCRR[CLKDIV] = 2.
Byte select timing1. Defines the state (0 or 1) of LBS during bus clock quarter phase 1
(LCRR[CLKDIV] = 4 or 8) or bus clock half phase 1 (LCRR[CLKDIV] = 2), in conjunction with
BR n [PS] and LA[24:25].
Byte select timing 2. Defines the state (0 or 1) of LBS during bus clock quarter phase 2
(LCRR[CLKDIV] = 4 or 8), in conjunction with BR n [PS] and LA[24:25]. Ignored when
LCRR[CLKDIV] = 2.
Byte select timing 3. Defines the state (0 or 1) of LBS during bus clock quarter phase 3
(LCRR[CLKDIV] = 4 or 8) or bus clock half phase 2 (LCRR[CLKDIV] = 2), in conjunction with
BR n [PS] and LA[24:25].
Byte select timing 4. Defines the state (0 or 1) of LBS during bus clock quarter phase 4
(LCRR[CLKDIV] = 4 or 8), in conjunction with BR n [PS] and LA[24:25]. Ignored when
LCRR[CLKDIV] = 2.
Figure 10-37 shows the RAM word fields. When
bits determine the state of UPM signals LCSn and
n
6 7 8 9
G0L
All zeros
23 24 25
REDO LOOP EXEN
All zeros
Description
Enhanced Local Bus Controller
10 11 12 13
G0H G1T1 G1T3
26 27 28 29
AMX NA UTA
14 15
G2T1 G2T3
30 31
TODT LAST
10-79