Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 754

Enhanced Three-Speed Ethernet Controllers
Table 15-15 describes the fields of the TCTRL register.
Bits Name
0–16 — Reserved
17 IPCSEN IP header checksum generation enable. When set, the eTSEC offloads IPv4 header checksum
generation. See
0 IP header checksum generation is disabled even if enabled in a transmit frame control block.
1 IP header checksum generation is performed for IPv4 headers as determined by the settings in the
current transmit frame control block.
18 TUCSEN TCP/UDP header checksum generation enable. When set, the eTSEC offloads TCP or UDP header
checksum generation. See
page
0 TCP or UDP header checksum generation is disabled even if enabled in a transmit frame control block.
1 TCP or UDP header checksum generation is performed as determined by the settings in the current
transmit frame control block.
19 VLINS VLAN (IEEE Std. 802.1Q) tag insertion enable. Applicable only for transmission through the Ethernet
MAC.
0 Do not insert a VLAN tag into the frame.
1 Insert a VLAN tag into the frame. If the frame FCB has a valid VLAN field, use the FCB to source the
VLAN control word, otherwise take the default VLAN control word from register DFVLAN.
20 THDF Transmit half-duplex flow control under software control for 10-/100-Mbps half-duplex media. This bit is
not self-resetting.
0 Disable back pressure
1 Back pressure is applied to media by raising carrier
21–26 — Reserved
27 RFC_PAUSE Receive flow control pause frame (written by the eTSEC). This read-only status bit is set if a flow control
pause frame was received and the transmitter is paused for the duration defined in the received pause
frame. This bit automatically clears after the pause duration is complete.
0 Pause duration complete.
1 Flow control pause frame received.
28 TFC_PAUSE Transmit flow control pause frame. Set this bit to transmit a PAUSE frame. If this bit is set, the MAC stops
transmission of data frames after the currently transmitting frame completes. Next, the MAC transmits a
pause control frame with the duration value obtained from the PTV register. The TXC event occurs after
sending the pause control frame. Finally, the controller clears TFC_PAUSE and resumes transmitting
data frames as before. Note that pause control frames can still be transmitted if the Tx controller is
stopped due to user assertion of DMACTRL[GTS] or reception of a PAUSE frame.
0 No request for Tx PAUSE frame pending or transmission complete.
1 Software request for Tx PAUSE frame pending.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-36
Table 15-15. TCTRL Field Descriptions
Section 15.6.3.2, "Transmit Path Off-Load and Tx PTP Packet Parsing," on page
Section 15.6.3.2, "Transmit Path Off-Load and Tx PTP Packet Parsing," on
15-161.
Description
15-161.
Freescale Semiconductor