Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 275

5.8.2.1 Power Management Controller Configuration Register (PMCCR)
The power management controller configuration register (PMCCR), shown in
whether only the PowerPC core will enter low power state upon quiesce request or additional parts of the
device will also enter low power state.
Offset 0x00B00
0
R
W
Reset
Figure 5-51. Power Management Controller Configuration Register
Table 5-5 defines the bit fields of PMCCR.
'
Bits Name
0–29 — Reserved. Write has no effect, read returns 0.
30 DLPEN DDR SDRAM low power enable
0 The DDR SDRAM memory controller is prevented from entering low power state.
1 The DDR SDRAM memory controller will enter low power state when the rest of the system enters low
power, according to SLPEN setting. DDR SDRAM will enter self-refresh mode (if enabled by
DDR_SDRAM_CFG[SREN] memory controller register) and DDR clocks (MCK n ) are shut off. This bit is
cleared when the device exits from low power state. Note that setting this bit without setting SLPEN has
no effect.
31 SLPEN System low power enable
0 The system is prevented from entering low power state.
1 The system will enter low power state when a quiesce request from the PowerPC core arrives. This bit
is cleared when the device exits from low power state.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
All zeros
Table 5-67. PMCCR Bit Settings
Description
System Configuration
Figure 5-51, controls
Access: Read/Write
29 30 31
DLPEN SLPEN
5-67