Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 198

Reset, Clocking, and Initialization
single crystal option, the frequency for SYS_CLK_IN must be chosen such that the USB reference will be
24 or 48 MHz when utilizing the divide by 1 or 2 option, that is, the SYS_CLK_IN must be 24 or 48 MHz.
If this option is used in PCI agent mode, the PCI clock supplied to device must still be chosen at the
appropriate frequencies mentioned above. In this case the PCI source clock would be tied to both
SYS_CLK_IN and PCI_CLK inputs. The clock source will need to meet the input clock specifications for
both SYS_CLK_IN and USB_CLK_IN.
For more details refer to
4.4.5 Ethernet Clocking
The device contains an integrated high speed serial/deserializing (SerDes) PHY block that provides an
SGMII interface to an external PHY. The SGMII PHY interface has its own PLL and requires a reference
clock which is 1 V signal that can either be single ended or differential. The SerDes PHY generates its own
transmit and receive sampling clock. The receive clock is re-created from the receive data.
When running in RGMII or RTBI modes (not using the SerDes) the Gigabit reference clock is the
GTX_CLK125 input on the eTSEC1 interface which is common to both eTSECs. This can either be a 2.5-
or 3.3-V signal.
For more information refer to
4.4.6 Real-Time Clock (RTC)
The source for the RTC can come from the internal system clock (csb_clk) through a divider circuit or from
an off-chip source. For more information refer to
4.5 Memory Map/Register Definitions
This section presents the memory maps and register descriptions for both reset and clocking.
4.5.1 Reset Configuration Register Descriptions
The reset configuration and status registers are shown in
Table 4-27. Reset Configuration and Status Registers Memory Map
Address
0x0_0900 Reset configuration word low register (RCWLR)
0x0_0904 Reset configuration word high register (RCWHR)
0x0_0908 Reserved, should be cleared
0x0_090C Reserved, should be cleared
0x0_0910 Reset status register (RSR)
0x0_0914 Reset mode register (RMR)
0x0_0918 Reset protection register (RPR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-32
Chapter 16, "Universal Serial Bus Interface."
Chapter 15, "Enhanced Three-Speed Ethernet Controllers."
Register
Section 5.5, "Real Time Clock Module (RTC)."
Table 4-27.
Access
R
R
—
—
R/W
R/W
R/W
Reset Section/Page
0x0000_0000 4.5.1.1/4-33
0x0000_0000 4.5.1.2/4-33
— —
— —
0x0000_0000 4.5.1.3/4-33
0x0000_0000 4.5.1.4/4-35
0x0000_0000 4.5.1.5/4-35
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