Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 622

PCI Bus Interface
Table 13-41. PCI Arbiter Control Register (PCIACR) Field Descriptions (continued)
Bits Name
6–4 PRI n
3–1 —
0 MPRI
13.3.3.26 Hot Swap Register Block
Figure 13-44 shows the hot swap register block fields.
Offset 0x48
31
R
—
W
Reset 0 0 0 0 0 0 0 0
Table 13-42 shows the bit settings of the Hot Swap register block.
Bits Name
31–24 —
23 INS
22 EXT
21–20 —
19 LOO
18 —
17 EIM
16 —
15–8 NXT_PTR
7–0 CAP_ID
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-40
Priority level for master n . When the PCI controller functions as the arbiter for the PCI bus, each
PRIn bit determines the arbitration priority level for the PCI master connected to the REQ n /GNT n
pair.
0 Low priority
1 High priority
Reserved
My priority. When the PCI controller functions as the arbiter for the PCI bus, this bit determines the
arbitration priority level for the PCI controller when it acts as a PCI master.
0 Low priority
1 High priority
24 23 22 21 20
INS EXT
—
w1c w1c
0 0 0 0
Figure 13-44. Hot Swap Register Block
Table 13-42. Hot Swap Register Block Field Descriptions
Reserved
Insertion status. Indicates that a card has been inserted. Write 1 to clear this bit.
Extraction status. Indicates that a card has been extracted. Write 1 to clear this bit.
Reserved
LED On/Off. Controls the LED when the hardware is in state H2
0 LED off
1 LED on
Reserved
ENUM mask. This bit masks the CPCI_HS_ENUM input.
0 Enabled
1 Masked
Reserved
Next pointer—hardwired to 0x80 to point to the address of the power management capability in the
PCI controller.
Capability ID for hot swap (hardwired to 0x06)
Description
19 18 17 16 15
LOO — EIM —
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Description
8 7
NXT_PTR CAP_ID
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0