Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 567

12.3.5.2 Inbound Doorbell Register (IDR)
IDR is accessible from the PCI bus and the CSB in both host and agent modes.
fields.
Offset: 0x068
31 30 29
R
IMC IDR30 IDR29 IDR28 IDR27 IDR26 IDR25 IDR24 IDR23 IDR22 IDR21 IDR20 IDR19 IDR18 IDR17 IDR16
W
Reset
15 14 13
R
IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9
W
Reset
Table 12-7 describes the IDR registers.
Bits Name
31 IMC Inbound machine check.
Write 1 from the PCI bus to set.
Write 1 from the CSB to clear.
Writing 0 has no effect.
Writing this bit from the PCI bus causes a machine check interrupt to be generated to the local processor.
30–0 IDR n Inbound doorbell n .
Write 1 from the PCI bus to set.
Write 1 from the CSB to clear.
Writing 0 has no effect.
Writing a bit in this register from the PCI bus causes an interrupt to be generated to the local processor.
12.3.6 Inbound Message Interrupt Status Register (IMISR)
The IMISR contains the interrupt status of the doorbell and message register events. Writing a 1 to IM1I
clears the bit. The events are generated by the PCI masters.
Figure 12-8 shows the IMISR fields.
Offset 0x080
31
R
W
Reset
Figure 12-8. Inbound Message Interrupt Status Register (IMISR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
28 27 26 25
12 11 10 9
Figure 12-7. Inbound Doorbell Register (IDR)
Table 12-7. IDR Field Descriptions
—
24 23 22 21
All zeros
8 7 6 5
IDR8 IDR7 IDR6 IDR5 IDR4
All zeros
Descriptions
All zeros
DMA/Messaging Unit
Figure 12-7 shows the IDR
Access: User read/write
20 19 18 17
4 3 2 1
IDR3 IDR2 IDR1 IDR0
Access: User Mixed
4 3 2 1
MCI IDI
—
16
0
0
IM1I
w1c
12-7