Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 541

Table 10-43 lists the bytes required on the data bus for read cycles.
Transfer
Size
Byte
Half Word
Word
1
Address state is the calculated address for port size.
10.5.4 Command Sequence Examples for NAND Flash EEPROM
In order to program the eLBC and FCM for executing NAND Flash command sequences, command codes
and pause states should be obtained from the relevant NAND Flash device data sheet and programmed into
FCM configuration registers. This section illustrates some common sequences for large-page,
multi-gigabit NAND Flash EEPROMs; however, details should be verified against manufacturers'
specific programming data.
Throughout these examples it is assumed that one or more banks of eLBC has been configured under FCM
control (BRn[MSEL] = 001), with base address, port size, ECC mode, and timing parameters configured
in accordance with the device's hardware specifications.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 10-43. Data Bus Drive Requirements For Read Cycles
Address
1
State
3 lsbs
0–7 8–15
000 OP0 —
001 — OP1
010 OP2 —
011 — OP3
100 OP4 —
101 — OP5
110 OP6 —
111 — OP7
000 OP0 OP1
001 — OP1
010 OP2 OP3
100 OP4 OP5
101 — OP5
110 OP6 OP7
000 OP0 OP1
100 OP4 OP5
Port Size/LAD Data Bus Assignments
16-Bit
16–23 24–31 0–7
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
OP0
OP1
OP2
OP4
OP5
OP6
OP0
OP4
Enhanced Local Bus Controller
8-Bit
8–15 16–23 24–31
10-93