Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 878

Enhanced Three-Speed Ethernet Controllers
Error
CRC error If a CRC error occurs, the controller sets RxBD[CR], closes the buffer, and sets IEVENT[RXF]. This
eTSEC relies on the statistics collector block to record the event. After receiving a frame with a CRC
error, the receiver then enters hunt mode.
Memory read error A system bus error occurred during a DMA transaction. The controller sets IEVENT[EBERR] and
discards the frame and increments the discarded frame counter (RDRP). In addition the
RSTAT[QHLT n ] bit is set. The halted queue resumes reception once the RSTAT[QHLT n ] bit is cleared.
Data parity error Data in the receive FIFO or filer table was potentially corrupted. The controller sets IEVENT[DPE], but
otherwise continues reception until halted explicitly.
Babbling receive error A frame is received that exceeds the MAC's maximum frame length. The controller sets
IEVENT[BABR] and continues.
15.6.3 TCP/IP Off-Load
Each eTSEC provides hardware support for accelerating the basic functions of TCP/IP packet transmission
and reception. By default, these features are disabled and must be explicitly enabled through RCTRL and
TCTRL. In this configuration, the eTSEC processes frames as vanilla Ethernet frames and none of the
multi-ring QoS/CoS receive services or per-frame VLAN insertion and deletion are available. Operate
eTSEC in this default configuration when using existing TCP/IP stack software that has not been modified
to take advantage of TOE.
TOE can be enabled independently for Rx and Tx and at various levels. Receive TOE functions are
controlled by RCTRL and transmit functions through a combination of TCTRL[TUCSEN] and the Tx
frame control block.
On receive, according to RCTRL[PRSDEP], eTSEC can parse frames at layer 2 of the stack only (Ethernet
headers and switching headers), layers 2 to 3 (including IPv4 or IPv6), or layers 2 to 4 (including TCP and
UDP). TOE provides protocol header recognition, header verification (IPv4 header checksum
verification), and TCP/UDP payload checksum verification including verification of associated
pseudo-header checksums. For large frames off-load of checksum verification saves a significant fraction
of the CPU cycles that would otherwise be spent by the TCP/IP stack. IP packet fragmentation and
re-assembly, and TCP stream establishment and tear-down are not performed in hardware. The frame
parser sets RQFPR[IPF] status flag encountering a fragmented frame. The frame parser in eTSEC searches
a maximum of 512 bytes from the start of a received frame when attempting to locate headers; headers
deeper than 512 bytes are assumed not to exist, and any associated receive status flags in the frame control
block remain cleared.
On transmit, TOE provides IPv4 and TCP/UDP header checksum generation. Like receive TOE,
checksum generation reduces CPU load significantly for TCP/IP stacks modified to exploit eTSEC TOE
functions. The eTSEC does not checksum transmitted packets with IPv6 routing headers or calculate
TCP/UDP checksums from IP fragments. If a transmitted TCP segment requires checksum generation but
IPv6 extension headers would prevent eTSEC from calculating the pseudo-header checksum, software can
calculate just the pseudo-header checksum in advance and supply it to the eTSEC as part of per-frame TOE
configuration.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-160
Table 15-151. Reception Errors (continued)
Description
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