Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 96

Overview
1.2.8 Integrated Programmable Interrupt Controller (IPIC)
The IPIC implements the necessary functions to provide a flexible solution for general-purpose interrupt
control. The IPIC includes the following features:
• Functional and programming models are compatible with the MPC8260 interrupt controller
• Support for external and internal discrete interrupt sources
• Support for one external (optional) and seven internal machine checkstop interrupt sources
• Programmable highest priority request
• Two programmable priority mixed groups of four on-chip and four external interrupt signals with
two priority schemes for each group: grouped and spread
• Two programmable priority internal groups of eight on-chip interrupt signals with two priority
schemes for each group: grouped and spread
• Priority interrupts can be programmed to support a critical (cint) or system management (smi)
interrupt type
• External and internal interrupts directed to a host processor
• Unique vector number for each interrupt source
• Ability to redirect interrupts to external PCI_INTA pin when in core disable mode
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1.2.9 Dual I C Interfaces
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The inter-IC (IIC or I C) bus is a two-wire—serial data (SDA) and serial clock (SCL)—bidirectional serial
bus that provides a simple, efficient method of data exchange between the system and other devices, such
as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. The two-wire bus
minimizes the interconnections between devices. The synchronous, multi-master bus of the I
connection of additional devices to the bus for expansion and system development.
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The I C controller is a true multi-master bus which includes collision detection and arbitration that
prevents data corruption if two or more masters attempt to control the bus simultaneously. This feature
allows for complex applications with multiprocessor control. The I
transmitter/receiver unit, clocking unit, and control unit. The I
on-chip filtering rejects spikes on the bus.
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The I C interfaces include the following features:
• Two-wire interface
• Multi-master operational
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection
• Software-programmable clock frequency
• Software-selectable acknowledge bit
• On-chip filtering for spikes on the bus
• Address broadcasting supported
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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C controller consists of a
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C unit supports general broadcast mode and
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C allows the
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