Page 1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual Supports MPC8313E MPC8313 MPC8313ERM Rev. 2 12/2008...
Page 2 +33 1 69 35 48 48 (French) or for any other application in which the failure of the Freescale Semiconductor product www.freescale.com/support could create a situation where personal injury or death may occur. Should Buyer...
Page 3 Related Documentation..................... lxxvi Conventions ........................lxxvi Signal Conventions ...................... lxxvii Acronyms and Abbreviations ..................lxxvii Chapter 1 Overview MPC8313E PowerQUICC II Pro Processor Overview ........... 1-1 MPC8313E Architecture Overview................. 1-7 1.2.1 Power Architecture Core ..................... 1-7 1.2.2 Security Engine......................1-10 1.2.3...
Page 4 Reset Configuration Word High Register (RCWHR)..........4-14 4.3.2.2.1 PCI Host/Agent Configuration ................4-16 4.3.2.2.2 Boot Memory Space (BMS) ................4-17 4.3.2.2.3 Boot Sequencer Configuration ................4-17 4.3.2.2.4 Boot ROM Location ..................4-18 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 5 Output Clock Control Register (OCCR)..............4-39 4.5.2.3 System Clock Control Register (SCCR)..............4-40 Chapter 5 System Configuration Introduction........................5-1 Local Memory Map Overview and Example ..............5-1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 6 System General Purpose Register Low (SGPRL) ..........5-17 5.3.2.2 System General Purpose Register High (SGPRH) ..........5-17 5.3.2.3 System Part and Revision ID Register (SPRIDR) ..........5-18 5.3.2.3.1 SPRIDR[PARTID] Coding ................5-18 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 7 RTC Operational Modes ..................5-41 5.5.7 RTC Programming Guidelines................... 5-42 Periodic Interval Timer (PIT) ..................5-42 5.6.1 PIT Overview......................5-42 5.6.2 PIT Features....................... 5-43 5.6.3 PIT Modes of Operation .................... 5-43 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 8 External Signal Description ..................5-65 5.8.2 PMC Memory Map/Register Definition ..............5-65 5.8.2.1 Power Management Controller Configuration Register (PMCCR)....... 5-66 5.8.2.2 Power Management Controller Event Register (PMCER)........5-67 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 viii Freescale Semiconductor...
Page 9 Arbitration Policy ...................... 6-10 6.3.1.1 Address Bus Arbitration with PRIORITY[0:1] ............. 6-11 6.3.1.2 Address Bus Arbitration with REPEAT ..............6-12 6.3.1.3 Address Bus Arbitration after ARTRY..............6-13 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 10 7.1.7.4 Clock Multiplier....................7-12 7.1.7.5 Core Performance Monitor ..................7-12 PowerPC Architecture Implementation ................. 7-13 Implementation-Specific Information................7-13 7.3.1 Register Model......................7-14 7.3.1.1 UISA Registers ...................... 7-16 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 11 Features ..........................8-4 Modes of Operation ......................8-4 8.3.1 Core Enable Mode ....................... 8-4 8.3.2 Core Disable Mode ...................... 8-5 External Signal Description ..................... 8-5 8.4.1 Overview........................8-5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 12 Machine Check Interrupts..................8-35 Chapter 9 DDR Memory Controller Introduction........................9-1 Features ..........................9-2 9.2.1 Modes of Operation ..................... 9-3 External Signal Descriptions ................... 9-3 9.3.1 Signals Overview......................9-3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 13 DDR SDRAM Refresh and Power-Saving Modes ..........9-45 9.5.8.2.1 Self-Refresh in Sleep Mode................9-47 9.5.9 DDR Data Beat Ordering................... 9-48 9.5.10 Page Mode and Logical Bank Retention ..............9-48 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xiii...
Page 14 Flash Instruction Register (FIR) ................10-35 10.3.1.19 Flash Command Register (FCR) ................. 10-36 10.3.1.20 Flash Block Address Register (FBAR)..............10-37 10.3.1.21 Flash Page Address Register (FPAR) ..............10-37 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 15 FCM Extended Read Hold Timing..............10-69 10.4.3.4 FCM Boot Chip-Select Operation ............... 10-69 10.4.3.4.1 FCM Bank 0 Reset Initialization ..............10-70 10.4.3.4.2 Boot Block Loading into the FCM Buffer RAM..........10-70 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 16 NAND Flash Soft Reset Command Sequence Example ........10-94 10.5.4.2 NAND Flash Read Status Command Sequence Example ........10-94 10.5.4.3 NAND Flash Read Identification Command Sequence Example ....... 10-94 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 17 12.3.5 Doorbell Registers ..................... 12-6 12.3.5.1 Outbound Doorbell Register (ODR)..............12-6 12.3.5.2 Inbound Doorbell Register (IDR)................12-7 12.3.6 Inbound Message Interrupt Status Register (IMISR) ..........12-7 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xvii...
Page 18 PCI_CONFIG_DATA..................13-14 13.3.1.3 PCI Interrupt Acknowledge Register (PCI_INT_ACK)........13-15 13.3.2 PCI Memory-Mapped Control and Status Registers ..........13-15 13.3.2.1 PCI Error Status Register (PCI_ESR) ..............13-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xviii Freescale Semiconductor...
Page 19 PCI Function Configuration Register ..............13-38 13.3.3.25 PCI Arbiter Control Register (PCIACR) ............. 13-39 13.3.3.26 Hot Swap Register Block..................13-40 13.3.3.27 PCI Power Management Register 0 (PCIPMR0) ..........13-41 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 20 Security Engine (SEC) 2.2 14.1 SEC 2.2 Architecture Overview ..................14-2 14.1.1 Descriptors ......................... 14-3 14.1.2 Execution Units (EUs) ....................14-5 14.1.2.1 Data Encryption Standard Execution Unit (DEU)..........14-5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 21 MDEU Interrupt Control Register (MDEUICR) ..........14-36 14.4.2.9 MDEU ICV Size Register ................... 14-37 14.4.2.10 MDEU End-of-Message Register (MDEUEMR)..........14-38 14.4.2.11 MDEU Context Registers ..................14-38 14.4.2.12 MDEU Key Registers ..................14-39 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 22 EU Assignment Status Register (EUASR) ............14-67 14.6.4.2 Interrupt Mask Register (IMR)................14-68 14.6.4.3 Interrupt Status Register (ISR) ................14-70 14.6.4.4 Interrupt Clear Register (ICR) ................14-71 14.6.4.5 Identification Register (ID).................. 14-73 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxii Freescale Semiconductor...
Page 23 Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7) ...... 15-45 15.5.3.2.10 Transmit Descriptor Base Address Registers (TBASE0–TBASE7) ....15-46 15.5.3.2.11 Transmit Timestamp Identification Register (TMR_TXTS1–2_ID)....15-47 15.5.3.2.12 Transmit Timestamp Register (TMR_TXTS1–2_H/L) ........15-47 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xxiii...
Page 24 (MAC01ADDR1–MAC15ADDR1)............15-78 15.5.3.5.16 MAC Exact Match Address 1–15 Part 2 Registers (MAC01ADDR2–MAC15ADDR2)............15-79 15.5.3.6 MIB Registers...................... 15-79 15.5.3.6.1 Transmit and Receive 64-Byte Frame Counter (TR64) ........15-80 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxiv Freescale Semiconductor...
Page 25 Transmit Jabber Frame Counter (TJBR) ............15-98 15.5.3.6.39 Transmit FCS Error Counter (TFCS) .............. 15-98 15.5.3.6.40 Transmit Control Frame Counter (TXCF)............15-99 15.5.3.6.41 Transmit Oversize Frame Counter (TOVR) ............ 15-99 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 26 TBI Receive Process..................15-122 15.5.4.2.1 Synchronization ..................... 15-123 15.5.4.2.2 Auto-Negotiation for 1000BASE-X.............. 15-123 15.5.4.3 TBI MII Set Register Descriptions ..............15-123 15.5.4.3.1 Control Register (CR)..................15-124 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxvi Freescale Semiconductor...
Page 27 Interrupt Coalescing By Timer Threshold ............. 15-157 15.6.2.11 Inter-Frame Gap Time ..................15-158 15.6.2.12 Internal and External Loop Back ............... 15-158 15.6.2.13 Error-Handling Procedure.................. 15-158 15.6.3 TCP/IP Off-Load ....................15-160 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xxvii...
Page 28 Receive Buffer Descriptors (RxBD)..............15-190 15.7 Initialization/Application Information ............... 15-192 15.7.1 Interface Mode Configuration ................15-192 15.7.1.1 MII Interface Mode.................... 15-193 15.7.1.2 RGMII Interface Mode ..................15-196 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxviii Freescale Semiconductor...
Page 29 Port Status and Control Register (PORTSC) ............16-26 16.3.2.15 On-The-Go Status and Control (OTGSC)—Non-EHCI........16-31 16.3.2.16 USB Mode Register (USBMODE)—Non-EHCI ..........16-34 16.3.2.17 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI ....16-35 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xxix...
Page 30 16.5.6.3 Transfer Overlay ....................16-65 16.5.7 Periodic Frame Span Traversal Node (FSTN)............16-66 16.5.7.1 FTSN Normal Path Pointer.................. 16-67 16.5.7.2 FSTN Back Path Link Pointer ................16-67 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 31 Rebalancing the Periodic Schedule ............... 16-104 16.6.12.3 Split Transaction Isochronous ................16-104 16.6.12.3.1 Split Transaction Scheduling Mechanisms for Isochronous ......16-105 16.6.12.3.2 Tracking Split Transaction Progress for Isochronous Transfers....16-108 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xxxi...
Page 32 Data Toggle......................16-134 16.8.3.2.1 Data Toggle Reset..................16-134 16.8.3.2.2 Data Toggle Inhibit ..................16-134 16.8.3.3 Device Operational Model For Packet Transfers ..........16-135 16.8.3.3.1 Priming Transmit Endpoints................16-135 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxxii Freescale Semiconductor...
Page 33 Multiple Transaction Translators..............16-152 16.9.2 Device Operation ....................16-152 16.9.3 Non-Zero Fields the Register File ................. 16-152 16.9.4 SOF Interrupt ......................16-152 16.9.5 Embedded Design ....................16-153 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xxxiii...
Page 34 Arbitration Procedure ....................17-13 17.4.2.1 Arbitration Control ....................17-14 17.4.3 Handshaking ......................17-14 17.4.4 Clock Control......................17-14 17.4.4.1 Clock Synchronization..................17-15 17.4.4.2 Input Synchronization and Digital Filter ............. 17-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxxiv Freescale Semiconductor...
Page 35 18.3.1.8 MODEM Control Registers (UMCR1 and UMCR2).......... 18-13 18.3.1.9 Line Status Registers (ULSR1 and ULSR2) ............18-14 18.3.1.10 MODEM Status Registers (UMSR1 and UMSR2) ..........18-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xxxv...
Page 36 SPI Mode Register (SPMODE) ................19-9 19.4.1.2 SPI Event Register (SPIE) ................... 19-11 19.4.1.3 SPI Mask Register (SPIM) .................. 19-12 19.4.1.4 SPI Command Register (SPCOM) ..............19-14 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxxvi Freescale Semiconductor...
Page 37 GPIO Interrupt Control Register (GPICR) ..............21-5 Appendix A Revision History Changes From Revision 1 to Revision 2 ................ A-1 Changes From Revision 0 to Revision 1 ..............A-23 Glossary Index MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xxxvii...
Page 38 Contents Paragraph Page Number Title Number MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xxxviii Freescale Semiconductor...
Page 39 DDR Local Access Window n Base Address Registers (DDRLAWBAR0– DDRLAWBAR1) ......................5-12 DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1) ..5-13 5-10 System General Purpose Register Low (SGPRL)..............5-17 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xxxix...
Page 40 Timers Non-Cascaded Mode Block Diagram ............... 5-62 5-49 Timer Pair-Cascaded Mode Block Diagram ................. 5-63 5-50 Timers Super-Cascaded Mode Block Diagram..............5-63 5-51 Power Management Controller Configuration Register ............5-66 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 41 System Error Status Register (SERSR)................. 8-22 8-17 System Error Mask Register (SERMR) ................8-24 8-18 System Error Control Register (SERCR)................8-24 8-19 System Internal Interrupt Force Register (SIFCR_H) ............8-25 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 42 DDR SDRAM Power-Down Mode ..................9-46 9-32 DDR SDRAM Self-Refresh Entry Timing ................9-47 9-33 DDR SDRAM Self-Refresh Exit Timing ................9-47 10-1 Enhanced Local Bus Controller Block Diagram..............10-1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xlii Freescale Semiconductor...
Page 43 GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8) ............10-52 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xliii...
Page 44 LBS Signal Selection ......................10-83 10-67 UPM Read Access Data Sampling..................10-86 10-68 Effect of LUPWAIT Signal ....................10-87 10-69 Multiplexed Address/Data Bus for 26-Bit Addressing ............10-88 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xliv Freescale Semiconductor...
Page 45 DMA Chain of Segment Descriptors .................. 12-19 13-1 PCI Controller Block Diagram ..................... 13-2 13-2 PCI Interface External Signals....................13-5 13-3 PCI_CONFIG_ADDRESS Register ................... 13-13 13-4 PCI_CONFIG_DATA ......................13-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 46 PCI Function Configuration Register ................. 13-38 13-43 PCI Arbiter Control Register (PCIACR) ................13-39 13-44 Hot Swap Register Block ....................13-40 13-45 PCI Power Management Register 0 (PCIPMR0)..............13-41 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xlvi Freescale Semiconductor...
Page 47 AESU Reset Control Register (AESURCR)............... 14-43 14-30 AESU Status Register (AESUSR) ..................14-44 14-31 AESU Interrupt Status Register (AESUISR)..............14-45 14-32 AESU Interrupt Control Register (AESUICR) ..............14-47 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xlvii...
Page 48 RCTRL Register Definition ....................15-48 15-23 RSTAT Register Definition ....................15-50 15-24 RXIC Register Definition ....................15-52 15-25 RQUEUE Register Definition..................... 15-53 15-26 RBIFX Register Definition ....................15-54 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 xlviii Freescale Semiconductor...
Page 49 Receive Pause Frame Packet Counter Register Definition ..........15-86 15-66 Receive Unknown OPCode Packet Counter Register Definition ........15-86 15-67 Receive Alignment Error Counter Register Definition............15-87 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor xlix...
Page 50 RQPRM Register Definition ..................... 15-109 15-104 RFBPTR0–RFBPTR7 Register Definition................ 15-110 15-105 TMR_CTRL Register Definition ..................15-111 15-106 TMR_TEVENT Register Definition................. 15-113 15-107 TMR_PEVENT Register Definition................. 15-115 15-108 TMR_PEMASK Register Definition ................15-116 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 51 Transmit Buffer Descriptor ....................15-187 15-147 Mapping of TxBDs to a C Data Structure................. 15-187 15-148 Receive Buffer Descriptor....................15-190 15-149 Mapping of RxBDs to a C Data Structure ................ 15-191 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 52 Isochronous Transaction Descriptor (iTD) ................. 16-50 16-39 Split-Transaction Isochronous Transaction Descriptor (siTD) ........... 16-53 16-40 Queue Element Transfer Descriptor (qTD)................. 16-57 16-41 Queue Head Layout ......................16-62 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 53 Cn Digital Filter Sampling Rate Register (I2CnDFSRR) ..........17-9 17-8 C Interface Transaction Protocol..................17-10 17-9 EEPROM Contents ......................17-17 17-10 EEPROM Data Format for One Register Preload Command..........17-18 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor liii...
Page 54 GPIO Data Register (GPDAT) ....................21-4 21-5 GPIO Interrupt Event Register (GPIER) ................21-4 21-6 GPIO Interrupt Mask Register (GPIMR)................21-5 21-7 GPIO Interrupt Control Register (GPICR) ................21-5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 55 Reset Configuration and Status Registers Memory Map............4-32 4-28 Reset Status Register Field Descriptions ................4-33 4-29 RMR Field Descriptions ....................... 4-35 4-30 RPR Bit Descriptions ......................4-36 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 56 DDRDSR Field Descriptions ....................5-28 5-32 WDT Register Address Map....................5-30 5-33 SWCRR Bit Settings ......................5-31 5-34 SWCNR Bit Settings......................5-32 5-35 SWSRR Bit Settings ......................5-33 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 57 Software-Controller Power-Down States—Basic Description ..........5-76 5-74 MPC8313E Agent Mode Wake-Up Support................. 5-80 5-75 MPC8313E Host Mode Wake-Up Support ................5-82 Arbiter Register Map ......................6-2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lvii...
Page 58 SMPRR_B Field Descriptions ....................8-20 8-19 SEMSR Field Descriptions ....................8-21 8-20 SECNR Field Descriptions ....................8-22 8-21 SERSR/SERMR/SERFR Bit Assignments ................8-23 8-22 SERSR Field Descriptions ....................8-23 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lviii Freescale Semiconductor...
Page 59 Example of Address Multiplexing for 32-Bit Data Bus Interleaving Between Two Banks with Partial Array Self Refresh Disabled............9-36 9-30 DDR SDRAM Command Table.................... 9-38 9-31 DDR SDRAM Interface Timing Intervals ................9-39 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 60 Boot Bank Field Values after Reset for GPCM as Boot Controller........10-56 10-35 FCM Chip-Select to First Command Timing..............10-65 10-36 FCM Command, Address, and Write Data Timing Parameters.......... 10-66 10-37 FCM Read Data Timing Parameters ................... 10-69 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 61 Signal Properties ........................13-4 13-3 PCI Interface Signals—Detailed Signal Descriptions ............13-5 13-4 PCI Configuration Access Registers................... 13-11 13-5 PCI Memory-Mapped Registers ..................13-12 13-6 PCI_CONFIG_ADDRESS Field Descriptions ..............13-13 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 62 Hot Swap Register Block Field Descriptions ..............13-40 13-43 PCIPMR0 Field Descriptions....................13-41 13-44 PCIPMR1 Field Descriptions....................13-42 13-45 PCI Command Definitions....................13-46 13-46 Special Cycle Commands ....................13-56 14-1 Example Descriptor....................... 14-4 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxii Freescale Semiconductor...
Page 63 Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers ....14-70 14-40 MCR Field Descriptions ..................... 14-74 15-1 eTSECn Network Interface Signal Properties ..............15-6 15-2 eTSEC Signals—Detailed Signal Descriptions ..............15-8 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lxiii...
Page 64 TMR_RXTS_H/L Register Field Descriptions..............15-64 15-40 MACCFG1 Field Descriptions ................... 15-67 15-41 MACCFG2 Field Descriptions ................... 15-69 15-42 IPGIFG Field Descriptions ....................15-70 15-43 HAFDUP Field Descriptions ....................15-71 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxiv Freescale Semiconductor...
Page 65 15-80 TBYT Field Descriptions....................15-91 15-81 TPKT Field Descriptions ....................15-92 15-82 TMCA Field Descriptions....................15-92 15-83 TBCA Field Descriptions....................15-93 15-84 TXPF Field Descriptions ....................15-93 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 66 TMR_ALARMn_H/L Register Field Descriptions ............15-120 15-123 TMR_FIPER Register Field Descriptions ................ 15-121 15-124 TMR_ETTS1-2_H Register Field Descriptions ............... 15-121 15-125 TBI MII Register Set......................15-123 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxvi Freescale Semiconductor...
Page 67 Transmit Data Buffer Descriptor (TxBD) Field Descriptions .......... 15-188 15-164 Receive Buffer Descriptor Field Descriptions ..............15-191 15-165 MII Interface Mode Signal Configuration ................ 15-193 15-166 Shared MII Signals......................15-194 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lxvii...
Page 68 16-26 ENDPTSETUPSTAT Register Field Descriptions.............. 16-35 16-27 ENDPTPRIME Register Field Descriptions ............... 16-35 16-28 ENDPTFLUSH Register Field Descriptions............... 16-36 16-29 ENDPTSTATUS Register Field Descriptions ..............16-37 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxviii Freescale Semiconductor...
Page 69 Interrupt IN/OUT Do Complete Split State Execution Criteria........16-103 16-69 Initial Conditions for OUT siTD TP and T-Count Fields ..........16-111 16-70 Transaction Position (TP)/Transaction Count (T-Count) Transition Table......16-111 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lxix...
Page 70 I2CnDFSRR Field Descriptions..................17-10 18-1 DUART Signal Overview ..................... 18-3 18-2 DUART Signals—Detailed Signal Descriptions ..............18-3 18-3 DUART Register Summary ....................18-4 18-4 URBR Field Descriptions ..................... 18-6 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 71 GPODR Bit Settings ......................21-3 21-5 GPnDAT Bit Settings ......................21-4 21-6 GPIER Bit Settings ....................... 21-4 21-7 GPIMR Bit Settings ......................21-5 21-8 GPICR Bit Settings ....................... 21-5 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lxxi...
Page 72 Tables Table Page Number Title Number MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxii Freescale Semiconductor...
Page 73 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lxxiii...
Page 74 Ethernet controllers on the MPC8313E. These controllers provide 10/100/1Gb Ethernet support with a set of media-independent interface options including MII, RMII, GMII, SGMII and RTBI. They are backward compatible with PowerQUICC III TSEC controllers. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxiv Freescale Semiconductor...
Page 75 Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy and David A. Patterson. • Computer Organization and Design: The Hardware/Software Interface, Second Edition, by David A. Patterson and John L. Hennessy. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lxxv...
Page 76 In some contexts, such as signal encodings, an unitalicized x indicates a don’t care An italicized x indicates an alphanumeric variable An italicized n indicates a numeric variable ¬ NOT logical operator MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxvi Freescale Semiconductor...
Page 77 ARC four execution unit Buffer descriptor BIST Built-in self test Collision detect Collision Communication processor module Cyclic redundancy check Carrier sense Coherent system bus CSMA Carrier-sense multiple access MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lxxvii...
Page 78 Instruction translation lookaside buffer Integer unit JTAG Joint Test Action Group LALE LBC external address latch enable Local bus controller Least recently used Least-significant byte Least-significant bit Load/store unit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxviii Freescale Semiconductor...
Page 79 RTBI Reduced ten-bit interface Real time clock module Receive RxBD Receive buffer descriptor Serial clock Serial data Start frame delimiter SGMII Serial gigabit media independent interface MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor lxxix...
Page 80 Universal asynchronous receiver/transmitter ULPI USB low-pin count interface User-programmable machine Universal serial bus UTMI USB transceiver macrocell interface Unshielded twisted pair Watchdog timer Zero bus turnaround MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 lxxx Freescale Semiconductor...
Page 81 MPC8313. Note that the MPC8313 does not support a security engine. The MPC8313E contains an embedded PowerPC™ e300c3 core built on Power Architecture ™ technology. MPC8313E PowerQUICC II Pro Processor Overview Figure 1-1 shows the major functional units within the MPC8313E. The e300c3 core in the MPC8313E, with its 16 Kbytes of instruction and 16 Kbytes of data cache, implements the PowerPC user instruction set architecture and provides hardware and software debugging support.
Page 82 • DDR SDRAM memory controller — Programmable timing supporting both DDR1 and DDR2 SDRAM — 16-/32-bit data interface, up to 333-MHz data rate — 512-Mbyte addressable space MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 83 — Full- and half-duplex Ethernet support (1000 Mbps supports only full-duplex): – IEEE Std. 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 84 — Designed to comply with Universal Serial Bus Revision 2.0 Specification — Supports operation as a stand-alone USB host controller – Supports USB root hub with one downstream-facing port MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 85 • Dual I C interfaces — Each controller operates up to 400 kHz — Two-wire interface — Multiple-master support — Master or slave I C mode support MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 86 — Real-time clock — Software watchdog timer — Two general-purpose timers • IEEE Std. 1149.1™ compliant JTAG boundary scan • Integrated PCI bus and SDRAM clock generation MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 87 As an added feature to the e300 core, the device can lock the contents of three of the four ways in the instruction and data cache (or an entire cache). For example, this allows embedded applications to lock MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 88 BPU, LSU, and SRU) operate independently and in parallel. Note that this is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 89 JTAG/COP Clock Multiplier Interface Touch Load Buffer Processor Logic Copy-Back Buffer Bus Interface 32-Bit Address Bus 64-Bit Data Bus Figure 1-2. MPC8313E Integrated e300c3 Core Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 90 The DDR memory controller includes the following features: • Support for DDR1 and DDR2 SDRAM • 16- or 32-bit SDRAM data bus • Programmable settings for meeting all SDRAM timing parameters MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-10 Freescale Semiconductor...
Page 91 On receive, packets may be distributed to any of the 64 virtual receive queues overlaid onto the 8 physical receive queues. A table-oriented queue filing strategy is provided based on 16 header fields or flags. Frame rejection is supported for filtering applications. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 1-11...
Page 92 When in host mode, the PCI controller supports external signal isolation, thus enabling power shut off to external devices • Supports PCI Power Management 1.2 • Supports PME generation (agent) and Wake on PME MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-12 Freescale Semiconductor...
Page 93 The host and device functions are both configured to support the following four types of USB transfers: • Bulk • Control • Interrupt • Isochronous TX Buffer Dual-Role Module (DR) RX Buffer DR Mux On-Chip PHY Figure 1-4. USB Controllers Port Configuration MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 1-13...
Page 94 — Data buffer controls activated on a per-bank basis — Up to 256-byte bursts, arbitrarily aligned — Automatic segmentation of large transactions into memory accesses optimized for bus width and addressing capability MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-14 Freescale Semiconductor...
Page 95 — Internal address multiplexing supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, and 256-Mbyte page banks • Optional monitoring of transfers between local bus internal masters and local bus slaves (local bus error reporting) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 1-15...
Page 96 Calling address identification interrupt • Bus busy detection • Software-programmable clock frequency • Software-selectable acknowledge bit • On-chip filtering for spikes on the bus • Address broadcasting supported MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-16 Freescale Semiconductor...
Page 97 Clear to send (CTS) and ready to send (RTS) MODEM control functions • Software-selectable serial-interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate) • Line status registers • Line-break detection and generation MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 1-17...
Page 98 Application Examples The internal features of the MPC8313E make it suitable for a wide variety of printer and network communication applications as described in this section. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-18 Freescale Semiconductor...
Page 99 (graphic processing ASIC) at a lower cost without the need to have separate a CPU and interface ASIC. At the same time, the system is required to consume low power. The MPC8313E provides several power management methods to reduce power consumption. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 1-19...
Page 100 Once the I/O processor detects data transfer through the LAN, USB and PCI or an interrupt from the push of a button on the panel, it quickly boots up the main CPU. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-20 Freescale Semiconductor...
Page 101 The trigger inputs and outputs enable coordination of other devices. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 1-21...
Page 102 Target applications for systems with IEEE Std. 1588 are test and measurement appliances and industrial control and automation. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-22 Freescale Semiconductor...
Page 103 Ethernet. Having an SGMII interface on the Gigabit Ethernet PHYs enables low overall power consumption. The MPC8313E also has superior PCI to memory performance. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 1-23...
Page 104 The trend in the industry will be more focused on providing ASSPs (MPEG processors, image processors, integrated digital TV processors, audio/video decoders). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 1-24 Freescale Semiconductor...
Page 105 This would allow for maintaining the legacy functionality when set to zero. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 106 0x0_3100–0x0_31FF I C2 controller 24 bytes 256 bytes 0x0_3200–0x0_32FF Reserved — 256 bytes 0x0_3300–0x0_33FF Reserved — 256 bytes 0x0_3400–0x0_37FF Reserved — 1 Kbyte 0x0_3800–0x0_3BFF Reserved — 1 Kbyte MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 107 0x1_A000–0x1_BFFF Reserved — 8 Kbytes 0x1_C000–0x1_FFFF Reserved — 16 Kbytes 0x2_0000–0x2_1FFF Reserved — 8 Kbytes 0x2_2000–0x2_2FFF Reserved — 4 Kbytes 0x2_3000–0x2_3FFF USB_DR module 1 Kbyte 4 Kbytes MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 108 0x0_0008 Alternate configuration base address register (ALTCBAR) 0x0000_0000 5.2.4.2/5-7 0x0_000C– Reserved — — — 0x0_001C 0x0_0020 eLBC local access window 0 base address register 0x0000_0000 5.2.4.3/5-8 (LBLAWBAR0) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 109 System part and revision ID register (SPRIDR) 0x80B0_0021 5.3.2.3/5-18 0x0010C Reserved — — — 0x00110 System priority configuration register (SPCR) 0x0000_0000 5.3.2.4/5-18 0x00114 System I/O configuration register low (SICRL) 0x0000_0000 5.3.2.5/5-21 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 110 0x0000_0000 5.6.5.5/5-47 0x14–0x1F Reserved — — Global Timers Module 1 0x00 Timer 1 and 2 global timers configuration register 0x00 5.7.5.1/5-55 (GTCFR1) 0x01–0x03 Reserved — — — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 111 System internal interrupt pending register (SIPNR_H) 0x0000_0000 8.5.3/8-11 0x0C System internal interrupt pending register (SIPNR_L) 0x0000_0000 8.5.3/8-11 0x10 System internal interrupt group A priority register 0x0530_9770 8.5.4/8-13 (SIPRR_A) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 112 Arbiter event response register (AERR) 0x0000_0000 6.2.8/6-10 Reset Module 0x0_0900 Reset configuration word low register (RCWLR) 0x0000_0000 4.5.1.1/4-33 0x0_0904 Reset configuration word high register (RCWHR) 0x0000_0000 4.5.1.2/4-33 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 113 DDR Memory Controller Memory Map 0x000 CS0_BNDS—Chip select 0 memory bounds 0x0000_0000 9.4.1.1/9-9 0x008 CS1_BNDS—Chip select 1 memory bounds 0x0000_0000 9.4.1.1/9-9 0x080 CS0_CONFIG—Chip select 0 configuration 0x0000_0000 9.4.1.2/9-10 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 114 C2 address register 0x00 17.3.1.1/17-5 0x0_3104 I2C2FDR—I C2 frequency divider register 0x00 17.3.1.2/17-6 0x0_3108 I2C2CR—I C2 control register 0x00 17.3.1.3/17-7 0x0_310C I2C2SR—I C2 status register 0x81 17.3.1.4/17-8 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-10 Freescale Semiconductor...
Page 115 ULCR—ULCR[DLAB] = x UART2 line control register 0x00 18.3.1.7/18-11 0x0_4604 UMCR—ULCR[DLAB] = x UART2 MODEM control register 0x00 18.3.1.8/18-13 0x0_4605 ULSR—ULCR[DLAB] = x UART2 line status register 0x60 18.3.1.9/18-14 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-11...
Page 116 Reserved — — — 0x0AC 0x0B0 LTESR—Transfer error status register 0x0000_0000 10.3.1.9/10-25 0x0B4 LTEDR—Transfer error disable register 0x0000_0000 10.3.1.10/10-27 0x0B8 LTEIR—Transfer error interrupt register 0x0000_0000 10.3.1.11/10-28 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-12 Freescale Semiconductor...
Page 117 Figure 19-11./19-15 0x038– Reserved — — — 0xFFF DMA Registers OMISR—Outbound message interrupt status register Mixed 0x0000_0000 12.3.1/12-3 0x0_8030 OMIMR—Outbound message interrupt mask register 0x0000_0000 12.3.2/12-4 0x0_8034 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-13...
Page 118 12.3.8.1/12-9 0x0_8280 DMASR3—DMA 3 status register 0x0000_0000 12.3.8.2/12-11 0x0_8284 DMACDAR3—DMA 3 current descriptor address register 0x0000_0000 12.3.8.3/12-12 0x0_8288 DMASAR3—DMA 3 source address register 0x0000_0000 12.3.8.4/12-13 0x0_8290 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-14 Freescale Semiconductor...
Page 119 POCMR4—PCI outbound comparison mask register 4 0x0000_0000 11.4.3/11-4 0x78 POTAR5—PCI outbound translation address register 5 0x0000_0000 11.4.1/11-3 0x80 POBAR5—PCI outbound base address register 5 0x0000_0000 11.4.2/11-3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-15...
Page 120 PCI inbound window attributes register 0 (PIWAR0) 0x0000_0000 13.3.2.13/13-24 0x7C– Reserved — — — 0xFF USB DR Controller Registers 0x2_3000– Reserved, should be cleared — — — 0x2_30FF MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-16 Freescale Semiconductor...
Page 121 ENDPTCTRL1—Endpoint control 1 0x0000_0000 16.3.2.23/16-39 0x2_31C8 ENDPTCTRL2—Endpoint control 2 0x0000_0000 16.3.2.23/16-39 0x2_31CA– Reserved — — — 0x2_31D4 0x2_3400 SNOOP1—Snoop 1 0x0000_0000 16.3.2.24/16-40 0x2_3404 SNOOP2—Snoop 2 0x0000_0000 16.3.2.24/16-40 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-17...
Page 122 TR03WT*—TxBD Rings 0–3 round-robin weightings 0x0000_0000 15.5.3.2.6/15-43 0x2_4144 TR47WT*—TxBD Rings 4–7 round-robin weightings 0x0000_0000 15.5.3.2.7/15-44 0x2_4148– Reserved — — — 0x2_4180 0x2_4180 TBDBPH*—Tx data buffer pointer high bits 0x0000_0000 15.5.3.2.8/15-45 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-18 Freescale Semiconductor...
Page 123 0x2_423C TBASE7*—TxBD base address of ring 7 0x0000_0000 15.5.3.2.10/15-46 0x2_4240– Reserved — — — 0x2_427C 0x2_4280 TMR_TXTS1_ID* - Tx timestamp identification tag (set 1) 0x0000_0000 15.5.3.2.11/15-47 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-19...
Page 124 0x2_439C RBPTR3*—RxBD pointer for ring 3 0x0000_0000 15.5.3.3.11/15-62 0x2_43A0 Reserved — — — 0x2_43A4 RBPTR4*—RxBD pointer for ring 4 0x0000_0000 15.5.3.3.11/15-62 0x2_43A8 Reserved — — — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-20 Freescale Semiconductor...
Page 125 MACCFG2—MAC configuration register 2 0x0000_7000 15.5.3.5.2/15-68 0x2_4508 IPGIFG—Inter-packet/inter-frame gap register 0x4060_5060 15.5.3.5.3/15-70 0x2_450C HAFDUP—Half-duplex control 0x00A1_F037 15.5.3.5.4/15-71 0x2_4510 MAXFRM—Maximum frame length 0x0000_0600 15.5.3.5.5/15-72 0x2_4514– Reserved — — — 0x2_451C MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-21...
Page 126 MAC04ADDR2*—MAC exact match address 4, part 2 0x0000_0000 0x2_4568 MAC05ADDR1*—MAC exact match address 5, part 1 0x0000_0000 0x2_456C MAC05ADDR2*—MAC exact match address 5, part 2 0x0000_0000 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-22 Freescale Semiconductor...
Page 127 TRMAX—Transmit and receive 1024- to 1518-byte frame 0x0000_0000 15.5.3.6.6/15-82 counter 0x2_4698 TRMGV—Transmit and receive 1519- to 1522-byte good 0x0000_0000 15.5.3.6.7/15-83 VLAN frame count eTSEC Receive Counters 0x2_469C RBYT—Receive byte counter 0x0000_0000 15.5.3.6.8/15-83 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-23...
Page 128 TJBR—Transmit jabber frame counter 0x0000_0000 15.5.3.6.38/15-98 0x2_471C TFCS—Transmit FCS error counter 0x0000_0000 15.5.3.6.39/15-98 0x2_4720 TXCF—Transmit control frame counter 0x0000_0000 15.5.3.6.40/15-99 0x2_4724 TOVR—Transmit oversize frame counter 0x0000_0000 15.5.3.6.41/15-99 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-24 Freescale Semiconductor...
Page 129 GADDR7—Group address register 7 0x0000_0000 0x2_48A0– Reserved — — — 0x2_4AFC eTSEC DMA Attribute Registers 0x2_4B00– Reserved — — — 0x2_4BF4 0x2_4BF8 ATTR—Attribute register 0x0000_0000 15.5.3.8.1/15-108 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-25...
Page 130 0x2_4E04 TMR_TEVENT*—Timestamp event register 0x0000_0000 15.5.3.10.2/15-112 0x2_4E08 TMR_TEMASK*—Timer event mask register 0x0000_0000 15.5.3.10.3/15-114 0x2_4E0C TMR_PEVENT*—Timestamp event register 0x0000_0000 15.5.3.10.4/15-115 0x2_4E10 TMR_PEMASK*—Timer event mask register 0x0000_0000 15.5.3.10.5/15-115 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-26 Freescale Semiconductor...
Page 131 REGISTERS 0x2_5FFF Security Engine Address Map Registers Controller Registers 0x3_0000– Reserved, should be cleared — — — 0x3_0FFF 0x3_1008 IMR—Interrupt mask register 0x0000_0000 14.6.4.2/14-68 _0000_0000 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-27...
Page 132 0x0000_0000 14.4.1.6/14-24 _0000_0000 0x3_2038 DEUICR—DEU interrupt control register 0x0000_0000 14.4.1.7/14-25 _0000_3000 0x3_2050 DEUEMR—DEU end-of-message register 0x0000_0000 14.4.1.8/14-27 _0000_0000 0x3_2100 DEUIV—DEU initialization vector register 0x0000_0000 14.4.1.9/14-27 _0000_0000 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-28 Freescale Semiconductor...
Page 133 0x0000_0000 14.4.2.4/14-32 _0000_0000 0x3_6018 MDEURCR—MDEU reset control register 0x0000_0000 14.4.2.5/14-33 _0000_0000 0x3_6028 MDEUSR—MDEU status register 0x0000_0000 14.4.2.6/14-34 _0000_0000 0x3_6030 MDEUISR—MDEU interrupt status register 0x0000_0000 14.4.2.7/14-35 _0000_0000 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 2-29...
Page 134 Cleared on read. eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the offsets are from 0x 2_5000 to 0x2_5FFF. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 2-30 Freescale Semiconductor...
Page 135 Refer to the MPC8313E Integrated Processor Hardware Specifications for a pinout diagram showing pin numbers and a listing of all the electrical and mechanical specifications. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 136 Local Bus LGPL2/LOE/LFRE Interface IIC1_SCL/CKSTOP_IN Interface 4 Signals LGPL3/LFWP IIC2_SCL/GPIO[11] 58 Signals LGPL4/LGTA/LUPWAIT/LFRB LGPL5 LCLK[0:1] LA[0:4]/MSRCID[0:4]/GPIO[0:4] LA[5]/MDVAL/GPIO[5] LA[6:7]/GPIO[6:7] LA[8:9]/GPIO[13:14] LA[10:15] Figure 3-1. MPC8313E Signal Groupings (1 of 2) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 137 Table 3-1. MPC8313E Signal Reference by Functional Block Functional No. of Table/ Alternate Name Description Block Signals Page Function(s) MDQ[0:31] DDR data 9-3/9-5 — MDM[0:3] DDR data mask 9-3/9-5 — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 138 PCI request 0 13-3/13-5 — PCI_REQ1 PCI request 1 13-3/13-5 CPCI_HS_ES PCI_REQ2 PCI request 2 13-3/13-5 — PCI_GNT0 PCI grant 0 13-3/13-5 — PCI_GNT1 PCI grant 1 13-3/13-5 CPCI_HS_LED MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 139 IIC1_SDA C serial data 17-1/17-3 CKSTOP_OUT/ TSEC_1588_TRIG1 IIC1_SCL C serial clock 17-1/17-3 CKSTOP_IN/ TSEC_1588_ALARM2 IIC2_SDA C serial data 17-1/17-3 PMC_PWR_OK GPIO10 IIC2_SCL C serial clock 17-1/17-3 GPIO11 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 140 TSEC_1588_PP1 data 2 TSEC1_TXD1 eTSEC1 transmit eTSEC1 15-2/15-8 TSEC_1588_PP2 data 2 TSEC1_TXD0 eTSEC1 transmit eTSEC1 15-2/15-8 USBDR_STP/ data 2 TSEC_1588_PP3 TSEC1_TX_EN eTSEC1 transmit eTSEC1 15-2/15-8 — enable MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 141 TSEC_1588_CLK 1588 external timer eTSEC 15-2/15-8 UART_SOUT2/LA10 reference clock input TSEC_1588_GCLK 1588 timers eTSEC 15-2/15-8 UART_SIN2/LA11 TSEC_1588_PP1 1588 timer pulse per eTSEC 15-2/15-8 UART_CTS2/LA12 period 1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 142 SD_PLL_TPA_ANA Analog test point for SGMII PHY 15-2/15-8 — SerDes PLL testing SD_PLL_TPD Digital test point for SGMII PHY 15-2/15-8 — SerDes PLL testing MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 143 LBC port address eLBC 10-2/10-5 TSEC_1588_CLK LA11 LBC port address eLBC 10-2/10-5 TSEC_1588_GCLK LA12 LBC port address eLBC 10-2/10-5 TSEC_1588_PP1 LA13 eLBC port address eLBC 10-2/10-5 TSEC_1588_PP2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 144 LCLK[0:1] eLBC clocks 0–1 eLBC 10-2/10-5 — LB_POR_CFG_BOOT Boot time ECC eLBC — TSEC_MDC _ECC_DIS checking USBDR_DRIVE_ USB VBus power 16-1/16-3 GTM1_TIN1/ VBUS enable GTM2_TIN2/ LSRCID0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-10 Freescale Semiconductor...
Page 145 USB PLL USB_PLL_GND Dedicated analog USB PHY 16-1/16-3 — ground for USB PLL USB_VSSA_BIAS Dedicated power for USB PHY 16-1/16-3 — USB bias circuit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-11...
Page 146 8-2/8-5 CKSTOP_IN/ GPIO12 Test clock JTAG 20-2/20-2 — Test data in JTAG 20-2/20-2 — Test data out JTAG 20-2/20-2 — Test mode select JTAG 20-2/20-2 — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-12 Freescale Semiconductor...
Page 147 GPIO — GTM1_TIN2/ I/O signal 18 GTM2_TIN1/ TSEC2_RX_CLK GPIO19 General-purpose GPIO — GTM1_TGATE2/ I/O signal 19 GTM2_TGATE1/ TSEC2_RX_DV GPIO[20:23] General-purpose GPIO — TSEC2_RXD[3:0] I/O signal 20-23 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-13...
Page 148 Reset and 4-3/4-5 IIC1_SDA/ clock TSEC_1588_TRIG1 CKSTOP_IN Clock stop in Reset and 4-3/4-5 IIC1_SCL/ clock TSEC_1588_ALARM2 CFG_CLKIN_DIV Configuration clock Reset and 3-3/3-29 — in division selection clock MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-14 Freescale Semiconductor...
Page 149 UART_SIN2/ valid TSEC_1588_GCLK LSRCID0 Memory debug Debug 10-2/10-5 GTM1_TIN1/ source ID 0 GTM2_TIN2/USBDR _DRIVE_VBUS LSRCID1 Memory debug Debug 10-2/10-5 GTM1_TGATE1/ source ID 1 GTM2_TGATE2/ USBDR_DRIVE_ VBUS MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-15...
Page 150 CompactPCI hot 13-3/13-5 PCI_GNT2 swap enumerator CPCI_HS_ES CompactPCI hot 13-3/13-5 PCI_REQ1 swap ejector switch CPCI_HS_LED CompactPCI hot 13-3/13-5 PCI_GNT1 swap LED EXT_PWR_CTRL External power 5-65/5-66 — control MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-16 Freescale Semiconductor...
Page 151 GPIO26 General-purpose GPIO — TSEC2_TX_EN I/O signal 26 GPIO27 General-purpose GPIO — TSEC2_TX_ER I/O signal 27 GPIO28 General-purpose GPIO — GTM1_TIN3/ I/O signal 28 GTM2_TIN4/ LSRCID4/SPIMOSI MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-17...
Page 152 Timer out 1 Global 5-54/5-52 LSRCID2/ Timers USBDR_PCTL0 GTM1_TOUT2/ Timer out 2/1 Global 5-54/5-52 GPIO24/ GTM2_TOUT1 Timers TSEC2_RX_ER GTM1_TOUT3 Timer out 3 Global 5-54/5-52 GPIO30/SPICLK Timers MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-18 Freescale Semiconductor...
Page 153 LBC port address eLBC 10-2/10-5 GPIO7/ TSEC_1588_TRIG2 LBC port address eLBC 10-2/10-5 GPIO13/ TSEC_1588_ALARM1 LBC port address eLBC 10-2/10-5 GPIO14/ TSEC_1588_PP3 LAD[0:15] LBC address/data eLBC 10-2/10-5 — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-19...
Page 154 ID 1 GTM2_TGATE2/ USBDR_DRIVE_ VBUS LSRCID2 Memory debug Debug 10-2/10-5 GTM1_TOUT1/ source ID 2 USBDR_PCTL0 LSRCID3 Memory debug Debug 10-2/10-5 LBC_PM_REF_10/ source ID 3 USBDR_PCTL1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-20 Freescale Semiconductor...
Page 155 MRAS DDR row address 9-3/9-5 — strobe MSRCID[0:4] Memory debug Debug 10-2/10-5 LA[0:4]/GPIO[0:4] source ID 0–4 MSRCID0 Memory debug Debug 10-2/10-5 UART_SOUT1 source ID 0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-21...
Page 156 PCI request 1 13-3/13-5 CPCI_HS_ES PCI_REQ2 PCI request 2 13-3/13-5 — PCI_RESET_OUT PCI reset 13-3/13-5 — PCI_SERR PCI system error 13-3/13-5 — PCI_STOP PCI stop 13-3/13-5 — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-22 Freescale Semiconductor...
Page 157 SGMII PHY 15-2/15-8 — reference clock (complement) SDAVDD Analog supply for SGMII PHY 15-2/15-8 — SerDes PLL SDAVSS Analog ground for SGMII PHY 15-2/15-8 — SerDes PLL MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-23...
Page 158 TSEC_1588_GCLK 1588 timers eTSEC 15-2/15-8 UART_SIN2/LA11 TSEC_1588_PP1 1588 timer pulse per eTSEC 15-2/15-8 UART_CTS2/LA12 period 1 TSEC_1588_PP2 1588 timer pulse per eTSEC 15-2/15-8 UART_RTS2/LA13 period 2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-24 Freescale Semiconductor...
Page 159 — enable TSEC1_TX_ER eTSEC1 transmit eTSEC1 15-2/15-8 TSEC_1588_ALARM2 error TSEC1_TXD0 eTSEC1 transmit eTSEC1 15-2/15-8 USBDR_STP/ data 2 TSEC_1588_PP3 TSEC1_TXD1 eTSEC1 transmit eTSEC1 15-2/15-8 TSEC_1588_PP2 data 2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-25...
Page 160 A, negative data (complement) Serial transmitter, SGMII PHY 15-2/15-8 — lane B, positive data Serial transmitter, SGMII PHY 15-2/15-8 — lane B, negative data (complement) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-26 Freescale Semiconductor...
Page 161 USB 2.0 VBUS line USB PHY — USB_VDDA Dedicated power for USB PHY — USB transceiver USB_VDDA_BIAS Dedicated ground USB PHY — for USB bias circuit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-27...
Page 162 XPADVSS[0:1] SerDes transceiver SGMII PHY 15-2/15-8 — pad ground See the MPC8313E Hardware Specification for resistor values. Table 3-3 for proper connection to power. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-28 Freescale Semiconductor...
Page 163 MCS[0:1] DDR chip select (2/DIMM) Both ‘Z’ MCKE DDR clock enable ‘0’ DDR differential clocks ‘0’ DDR differential clocks ‘1’ MODT[0:1] DRAM on-die termination Both ‘0’ MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-29...
Page 164 This pin should be pulled high during a hard reset for proper functionality of the device since it has a weak internal pull up. No external pull-down resistors are allowed to be mounted on this net. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-30 Freescale Semiconductor...
Page 165 Timing This signal should be connected to pull-up or pull-down on the board. The signal needs to be valid at all times and static. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 3-31...
Page 166 Signal Descriptions MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 3-32 Freescale Semiconductor...
Page 167 PCI_CLK (PCI agent mode) cycles. Requirements An open-drain signal. An external pull-up is required. Reset State Output, driven low during power-on and hard reset flows. High impedance after reset flow completes. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 168 Refer to the hardware specifications for proper resistors values to pull reset configuration signals high or low. Reset State Always input MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 169 Requirements Should be tied low if unused, for example when the clock is provided through USB_CR_CLK_IN or when derived from the system clock. Reset State Always input. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 170 The device has several inputs to the reset logic: • Power-on reset (PORESET) • External hard reset (HRESET) • External soft reset (SRESET) • Software watchdog reset • System bus monitor reset • Checkstop reset MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 171 A soft reset causes a reset exception to the e300 core but does not reset other device logic. Table 4-4 identifies the reset actions for each reset source. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 172 (CFG_RESET_SOURCE, CFG_CLKIN_DIV). 4. The system negates PORESET after at least 32 stable SYS_CLK_IN (PCI host mode) or PCI_CLK (PCI agent mode) clock cycles. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 173 14. The PCI interface can now accept external requests, if enabled, and the boot vector fetch by the core can proceed, if enabled. The device is now in its ready state. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 174 Because the device does not sample the reset configuration input signals (CFG_RESET_SOURCE, CFG_CLKIN_DIV) during a hard reset flow, setting a new value on those signals (other than that set during power-on reset) has no effect. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 175 While the PORESET and HRESET signals are asserted, all other signal drivers connected to these signals must be in the high-impedance state. Refer to the hardware specifications for proper resistor values for pulling reset configuration signals high or low. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 176 1011 Hard-coded option 3. Reset configuration word is not loaded. 1100 Hard-coded option 4. Reset configuration word is not loaded. 1101 Reserved 1110 Reserved 1111 Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-10 Freescale Semiconductor...
Page 177 (Agent Mode) PCI_CLK Cycles μ 33 MHz 33 MHz 0000 15210 (RCW loaded from NOR Flash) μ 66 MHz 66 MHz 1000–1100 15380 (use hard coded RCW) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-11...
Page 178 Reset configuration word low register (RCWLR) • Reset configuration word high register (RCWHR) • Reset status register (RSR) • System PLL mode register (SPMR) Section 4.5, “Memory Map/Register Definitions.” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-12 Freescale Semiconductor...
Page 179 4-9, establishes the clock ratio between the SYS_CLK_IN signal and the internal csb_clk of the device. csb_clk drives internal units and feeds the e300 core PLL. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-13...
Page 180 CORE Field — PCIARB — BOOTSEQ SWEN ROMLOC RLEXT — — Field TSEC1M TSEC2M — TLE LALE — Figure 4-4. Reset Configuration Word High Register (RCWHR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-14 Freescale Semiconductor...
Page 181 ROMLOC Boot ROM interface location. This bit combined with bit RLEXT determines where the device boots from. See Section 4.3.2.2.4, “Boot ROM Location,” for more information. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-15...
Page 182 Section 4.3.2.2, “Reset Configuration Word High Register (RCWHR)”), the boot ROM should not be located on the PCI interface because the device is not enabled to master reads onto the PCI bus. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-16 Freescale Semiconductor...
Page 183 C addressing mode is used. Boot sequencer is enabled and loads configuration information from a ROM on the I C interface. A valid ROM must be present. Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-17...
Page 184 The local access window of the selected boot ROM interface is enabled and initialized with the proper base address and size, as described in Section 5.2, “Local Memory Map Overview and Example.” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-18 Freescale Semiconductor...
Page 185 The function of these signals can be changed by writing to this register during system initialization. See Section 5.3.2.6, “System I/O Configuration Register High (SICRH).” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-19...
Page 186 Table 4-18. e300 Core True Little-Endian Reset Configuration Value Word High Register Field Name Meaning (Binary) (RCWHR) Bit Big-endian mode True little-endian mode MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-20 Freescale Semiconductor...
Page 187 (RCWL and RCWH). Table 4-21. Local Bus Reset Configuration Words Data Structure EEPROM Data Bits EEPROM Address [0:7] [8:15] [16:23] [24:31] 0x00 RCWL[0:7] 0x04 0x08 RCWL[8:15] 0x0C MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-21...
Page 188 CFG_RESET_SOURCE Meaning BR0[PS] BR0[MSEL] OR0[SCY] OR0[PGS] 0000 NOR Flash 1111 0001 NAND Flash, 8 bit, 0010 small page 0101 NAND Flash, 8 bit, 0010 large page MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-22 Freescale Semiconductor...
Page 189 (RCWLR) and reset configuration word high register (RCWHR) respectively (see Section 4.5.1.1, “Reset Configuration Word Low Register (RCWLR),” Section 4.5.1.2, “Reset Configuration Word High Register (RCWHR)”). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-23...
Page 190 CRC. In this example, it is assumed that the EEPROM contains information additional to the reset configuration words, which should be loaded in the functional state after the device completes its reset flow. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-24 Freescale Semiconductor...
Page 191 C boot sequencer can be caused by an incorrect EEPROM data structure or I C bus problem. If a reset configuration load failure occurs, due to preamble fail or any other MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-25...
Page 192 These values select hard-coded reset configuration words options, as described in Section 4.3.1.1, “Reset Configuration Word Source.” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-26 Freescale Semiconductor...
Page 193 Table 4-25. Examples For Hard-Coded Reset Configuration Words Usage CFG_RESET_SOURCE[0:3] 1000 1001 1010 1011 1100 PCI_CLK (MHz) csb_clk (MHz) DDR controller clock (MHz) Core clock (MHz) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-27...
Page 194 SYS_CLK_IN must be tied to quiet ground. Similarly, if USB_CLK_IN is used as the USB clock, USB_CR_CLK_IN (crystal input) must be tied to quiet ground; otherwise, USB_CLK_IN must be tied to quiet ground. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-28 Freescale Semiconductor...
Page 195 125-MHz source Figure 4-7. Clock Subsystem Block Diagram The primary clock input to this device is PCI_CLK. This clock is the reference to the system APLL. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-29...
Page 196 The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-30 Freescale Semiconductor...
Page 197 This allows for a single crystal or clock input to supply both system and USB references. The USB reference clock can be provided with a divide by 1 or 2 from these inputs (see Figure 4-7). When using the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-31...
Page 198 Reserved, should be cleared — — — 0x0_0910 Reset status register (RSR) 0x0000_0000 4.5.1.3/4-33 0x0_0914 Reset mode register (RMR) 0x0000_0000 4.5.1.4/4-35 0x0_0918 Reset protection register (RPR) 0x0000_0000 4.5.1.5/4-35 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-32 Freescale Semiconductor...
Page 199 Reset configuration word source. Reflects the value of CFG_RESET_SOURCE input signal during the reset flow. See Section 4.3.1.1, “Reset Configuration Word Source,” on page 4-10. Changing this field has no effect. 4–14 — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-33...
Page 200 HRS is cleared by writing a 1 (writing zero has no effect). 0 No hard reset event. 1 Hard reset event. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-34 Freescale Semiconductor...
Page 201 (RCR). To disable a write to the reset control register (RCR), the user should write a 1 to RCER[CRE]. Address 0x0_0918 Access: User read/write RCPW Reset All zeros RCPW Reset All zeros Figure 4-10. Reset Protection Register (RPR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-35...
Page 202 SWHR Software hard reset. Setting this bit causes the device to begin a hard reset flow. This bit returns to its reset state during the reset sequence, so reading it always returns all zeros. — Reserved. This bit should never be set. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-36 Freescale Semiconductor...
Page 203 It may hold values different than those in the RCWLR after a a hard reset sequence. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-37...
Page 204 CFG_CLKIN_DIV input signal during the reset flow. 9–15 COREPLL Core PLL configuration. See the hardware specifications for this device 16–31 — Reserved, should be cleared. — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-38 Freescale Semiconductor...
Page 205 Enable/Disable LCLK[0] pin clock out 0 Disable LCLK[0] 1 Enable LCLK[0] LCLK1OE Enable/Disable LCLK[1] pin clock out 0 Disable LCLK[1] 1 Enable LCLK[1] 26–31 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-39...
Page 206 10 USB DR clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than the USB DR). Note: 11USB DR clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the USB DR). 12–14 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-40 Freescale Semiconductor...
Page 207 PCI clock mode. Define the clock mode for all of the PCI complex - PCI and DMA. 0 PCI complex clocks are disabled. 1 PCI complex clocks are enabled. 16–31 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 4-41...
Page 208 Reset, Clocking, and Initialization MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 4-42 Freescale Semiconductor...
Page 209 Table 5-1. Local Access Windows Target Interface Window Number Target Interface Comments Configuration registers (IMMR) Fixed 1-Mbyte window size Local bus — Local bus — Local bus — Local bus — — — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 210 Local bus 0xA000_0000 512 Mbytes 0xC000_0000 256 Mbytes Local bus 0xFF40_0000 1 Mbyte Configuration registers (IMMR) 0xFF80_0000 8 Mbytes Local bus boot ROM Flash 4, 6, 8 Unused MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 211 The number of bits used in the comparison is dictated by each window’s size attribute. When an address hits within a window, the transaction is directed to the appropriate target. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 212 0x0_0008 Alternate configuration base address register (ALTCBAR) 0x0000_0000 5.2.4.2/5-7 0x0_000C– Reserved — — — 0x0_001C 0x0_0020 eLBC local access window 0 base address register (LBLAWBAR0) 0x0000_0000 5.2.4.3/5-8 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 213 Depends on reset configuration word high values. See Section 5.2.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,” details. Depends on reset configuration word high values. See Section 5.2.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,” for details. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 214 The IMMRBAR is shown in Figure 5-2. Offset 0x00 Access: User Read/Write BASE_ADDR — Reset — Reset All zeros Figure 5-2. Internal Memory Map Registers’ Base Address Register (IMMRBAR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 215 BASE_ADDR Identifies the12 most-significant address bits of an alternate base address used for boot sequencer configuration accesses. 12–31 — Reserved. Write has no effect, read returns 0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 216 LBLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word high BMS field. Table 5-8 defines the reset value of LBLAWBAR0[BASE_ADDR]. ‘ Table 5-8. LBLAWBAR0[BASE_ADDR] Reset Value RCWHR[BMS] BASE_ADDR Reset Value 0x00000 0xFF800 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 217 101–111 e300c3 core boot performed from a local bus device. Local bus 8-Mbyte (22+1) ) local access window is enabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 218 PCILAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word high BMS field. Table 5-12 defines the reset value of PCILAWBAR0[BASE_ADDR]. Table 5-12. PCILAWBAR0[BASE_ADDR] Reset Value PCILAWBAR0[BASE_ADDR] RCWHR[BMS] Reset Value 0x00000 0xFF800 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-10 Freescale Semiconductor...
Page 219 PCI device. (22+1) e300c3 core boot performed from a PCI device. PCI 8-Mbyte (2 ) local access window is enabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-11...
Page 220 DDRLAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word high BMS field. Table 5-16 defines the reset value DDRLAWBAR0. Table 5-16. DDRLAWBAR0[BASE_ADDR] Reset Value DDRLAWBAR0[BASE_ADDR] RCWHR[BMS] Reset Value 0x00000 0xFF800 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-12 Freescale Semiconductor...
Page 221 DDRLAWBAR0[SIZE] reset value, and DDRLAWAR0 is enabled according to the value set in the reset configuration word high ROMLOC and RLEXT field. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-13...
Page 222 The local bus controller has base registers that perform a similar function. The PCI interface has outbound address translation units that map the local address into an external address space. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-14 Freescale Semiconductor...
Page 223 “Internal Memory Map Registers Base Address Register (IMMRBAR).” The default value for the IMMRBAR is 0xFF40_0000. NOTE The internal memory map window is always the highest priority local access window. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-15...
Page 224 DDR debug status register (DDRDSR) 0x3300_0000 5.3.2.9/5-29 0x00130–0x Reserved — — — 0014C 0x00150–0x Reserved — — — 001FC Depends on the reset configuration word high configuration values. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-16 Freescale Semiconductor...
Page 225 Figure 5-11. System General Purpose Register High (SGPRH) Table 5-22 defines the bit fields of SGPRH. ‘ Table 5-22. SGPRH Bit Settings Bits Name Description 0–31 General purpose MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-17...
Page 226 The system priority and configuration register (SPCR), shown in Figure 5-13, controls the priority of requests for transactions on the internal system bus. This priority is considered by the system arbiter MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-18 Freescale Semiconductor...
Page 227 (for example, FIFOs in which reading a byte may advance some internal counter). 0 No performance enhancement. 1 Performance enhancement by speculative reading is enabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-19...
Page 228 10 Level 2 11 Level 3 (highest priority) 24-31 — Reserved, should be cleared. Table 5-27. CFG_RESET_SRC Values CFG_RESET_SRC SPCR[0] SPCR[1] 0000 1000 1001 1010 1011 1100 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-20 Freescale Semiconductor...
Page 229 0b0/0b00 0b1/0b01 0b10 0b11 Value Value Bits Group Pin Function 0 Pin Function 1 Pin Function 2 Pin Function 3 0–1 Reserved — — — — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-21...
Page 230 GPIO[31] 14–19 Reserved — — — — 20–21 USBDR GTM1_TIN1/GTM2_TIN2 LSRCID0 USBDR_DRIVE_VBU — GTM1_TGATE1/GTM2_T LSRCID1 USBDR_PWRFAULT — GATE2 GTM1_TOUT1 LSRCID2 USBDR_PCTL0 — — LSRCID3 USBDR_PCTL1 — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-22 Freescale Semiconductor...
Page 231 TSEC1M and TSEC2M fields settings in the reset configuration word high in order to select the correct output buffer impedance for full or reduced TSEC pin mode. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-23...
Page 232 Value Bits Group Pin Function 0 Pin Function 1 Pin Function 2 Pin Function 3 0–5 Reserved — — — — INTR_A IRQ_B3 CKSTOP_OUT — — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-24 Freescale Semiconductor...
Page 233 20–21 ETSEC2_F TSEC2_RX_DV GTM1_TGATE2/GTM — GPIO[19] 00 RTBI 2_TGATE1 11 Else 22–23 ETSEC2_G TSEC2_RX_ER GTM1_TOUT2 GTM2_TOUT1 GPIO[24] 00 RTBI 11 Else TSEC2_TX_CLK — — GPIO[25] — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-25...
Page 234 CFG_LBIU_MUX_EN must be asserted during power-on reset to select timer functionality. CFG_LBIU_MUX_EN=0 bypasses SICRH/SICRL register control and selects Pin Function 0 for these pads. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-26 Freescale Semiconductor...
Page 235 5.3.2.8 DDR Control Driver Register (DDRCDR) The DDR control driver register (DDRCDR) contains bits that allow control over the driver of the DDR SDRAM controller. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-27...
Page 236 Disable memory transaction reordering 0 Memory transaction reordering enabled 1 Memory transaction reordering disabled Q_DRN 0 Drain queue before sleep disable 1 Drain queue before sleep enable MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-28 Freescale Semiconductor...
Page 237 To prevent a reset, software must periodically restart the countdown. The WDT is responsible for asserting a hardware reset or machine-check interrupt (mcp) if the software fails to service MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-29...
Page 238 (mcp) • WDT prescaled/non-prescaled clock mode: The WDT counter clock can be prescaled by programming the SWCRR[SWPR] bit, which controls the divide-by-65,536 of the WDT counter. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-30 Freescale Semiconductor...
Page 239 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high). Figure 5-19. System Watchdog Control Register (SWCRR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-31...
Page 240 SWCNR is a read-only register. Writes to SWCNR have no effect and terminate without transfer error exception. Offset 0x8 Access: Read only 15 16 SWCN — Reset 0 Figure 5-20. System Watchdog Count Register (SWCNR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-32 Freescale Semiconductor...
Page 241 The user should periodically write 0x556C followed by 0xAA39 to this register to prevent a software watchdog timer timeout. SWSRR[WS] can be written at any time, but returns all zeros when read. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-33...
Page 242 Waiting for 0x556C 0xAA39 / Reload Not 0x556C / Do Not Reload Not 0xAA39 / Do Not Reload Figure 5-22. Software Watchdog Timer Service State Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-34 Freescale Semiconductor...
Page 243 (mcp), programmed in SWCRR[SWRI]. According to the value of SWCRR[SWRI], the WDT timer causes a hard reset or machine check interrupt to the core. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-35...
Page 244 (RTLDR). It can also be programmed to generate an interrupt every second. The real time counter control register (RTCTR) is used to enable or disable the various timer functions. The real time counter event MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-36 Freescale Semiconductor...
Page 245 Table 5-37. RTC Signal Properties Name Port Function Reset Pull Up RTC_CLK RTC_CLK Real time clock input. — Table 5-38 provides a detailed description of the external RTC signal. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-37...
Page 246 The register can be read at any time. Offset 0x00 Access: Read/Write — CLEN CLIN — AIM SIM Reset All zeros Figure 5-25. Real Time Counter Control Register (RTCNR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-38 Freescale Semiconductor...
Page 247 RTLDR. Table 5-41. RTLDR Bit Settings Bits Name Description 0–31 CLDV Contains the 32-bit value to be loaded in the 32-bit RTC counter. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-39...
Page 248 0–31 CNTV RTC counter value field. RTCTR[CNTV] contains the current value of the time counter. This is a read-only field. Writes have no effect on RTCTR[CNTV]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-40 Freescale Semiconductor...
Page 249 Table 5-45. RTALR Bit Settings Bits Name Description 0–31 ALRM RTC alarm value. The alarm interrupt is generated when the value of the RTC counter equals RTALR[ALRM]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-41...
Page 250 — RTC disable mode (RTCNR[CLEN] = 0) When the RTC’s clock is disabled, counter maintains its old value (default). — RTC enable mode (RTCNR[CLEN] = 1) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-42 Freescale Semiconductor...
Page 251 5.6.1 PIT Overview The periodic interval timer (PIT) that generates periodic interrupts for a real-time operating system or an application software. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-43...
Page 252 There is one distinct external input signal (PIT clock), defined in Table 5-46. Table 5-46. PIT Signal Properties Name Port Function Reset Pull Up PIT_CLK PIT_CLK Periodic interval timer. — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-44 Freescale Semiconductor...
Page 253 PIT functions. The register can be read at any time. Offset 0x00 Access: Read/Write — CLEN CLIN — Reset All zeros Figure 5-33. Periodic Interval Timer Control Register (PTCNR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-45...
Page 254 PTLDR. Table 5-50. PTLDR Bit Settings Bits Name Description 0–31 CLDV Contains the 32-bit value to be loaded in a 32-bit PIT counter. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-46 Freescale Semiconductor...
Page 255 The register can be read at any time. PTEVR bits are cleared by writing ones. Writing zeros does not affect the value of the status bits. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-47...
Page 256 PERIODIC Interrupt PTCNR[PIM] PTPSR[PRSC] PTCNR[CLIN] PTLDR[CLDV] PTEVR[PIF] Clock Clock 32-Bit 32-Bit Prescaler Counter Disable System Clocking PTCTR[CNTV] PTCNR[CLEN] Figure 5-38. Periodic Interval Timer Functional Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-48 Freescale Semiconductor...
Page 257 64-bit timer. Each GTM timer consists of a timer prescale register (GTPSR), a timer mode register (GTMDR) a timer capture register (GTCPR), a timer counter register (GTCNR), a timer reference register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-49...
Page 258 3-nanosecond timer resolution (at 167-MHz bus clock and no prescaler) • Resolution and maximum period can be traded off by selecting prescaler divisor • Three programmable input clock sources for the timer prescalers MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-50 Freescale Semiconductor...
Page 259 Free run reference mode. The corresponding timer count continues to increment after the reference value is reached. • Reset reference mode. The corresponding timer count is reset immediately after the reference value is reached. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-51...
Page 260 Global timer 1 counter output signal TOUT2 TOUT2 Global timer 2 counter output signal TOUT3 TOUT3 Global timer 3 counter output signal TOUT4 TOUT4 Global timer 4 counter output signal MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-52 Freescale Semiconductor...
Page 261 All GTM registers are 8 or 16 bits wide, located on 8-bit or 16-bit address boundaries, and should only be accessed as 8-bit or 16-bit quantities. All addresses used in this chapter are offsets from GPT Base, as defined in Chapter 2, “Memory Map.” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-53...
Page 262 General Purpose (Global) Timer Module 2: All registers defined for GTM1 are also defined for GTM2; the base address of GTM2 registers is 0x0_06 nn . MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-54 Freescale Semiconductor...
Page 263 0 Reset the timer 2, including GTMDR2, GTRFR2, GTCNR2, GTCPR2, and GTEVR2 (a software reset is identical to an external reset). 1 Enable the corresponding timer if the STP2 bit is cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-55...
Page 264 The GTCFR2 register is shown in Figure 5-41. Offset 0x04 Access: Read/Write PCAS SCAS STP4 RST4 STP3 RST3 Reset All zeros Figure 5-41. Global Timers Configuration Register 2 (GTCFR2) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-56 Freescale Semiconductor...
Page 265 0 Reset the timer 3, including GTMDR3, GTRFR3, GTCNR3, GTCPR3, and GTEVR3 (a software reset is identical to an external reset). 1 Enable the corresponding timer if the STP3 bit is cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-57...
Page 266 0 Free run. The timer count continues to increment after the reference value is reached. 1 Restart. The timer count is reset immediately after the reference value is reached. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-58 Freescale Semiconductor...
Page 267 GTMDRn[CE]. Offset 0x18(GTCPR1) 0x28(GTCPR3) Access: Read only 0x1A(GTCPR2) 0x2A(GTCPR4) Reset All zeros Figure 5-44. Global Timers Capture Registers (GTCPR1–GTCPR4) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-59...
Page 268 Offset 0x30(GTEVR1) 0x34(GTEVR3) Access: w1c 0x32(GTEVR2) 0x36(GTEVR4) — Reset All zeros Figure 5-46. Global Timers Event Registers (GTEVR1—GTEVR4) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-60 Freescale Semiconductor...
Page 269 GTMDRn SPS prescale r This gives a total prescale range from 1 (GTPSRn[PPS] = 0x00, GTMDRn[SPS] = 0x00) to 65,536 (GTPSRn[PPS] = 0xFF, GTMDR[SPS] = 0xFF). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-61...
Page 270 (TGATEn) that controls the timers. The type of transition triggering the capture is selected by the corresponding GTMDRn[CE] bits. Upon a capture or reference MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-62 Freescale Semiconductor...
Page 271 GTRFR1, GTCPR1, GTCNR1 GTRFR2, GTCPR2, GTCNR2 Capture Capture Timer3 Timer4 Clock Clock GTRFR3, GTCPR3, GTCNR3 GTRFR4, GTCPR4, GTCNR4 Capture Capture Figure 5-48. Timers Non-Cascaded Mode Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-63...
Page 272 D[47–32] Timer3 Timer4 Clock GTRFR3, GTCPR3, GTCNR3 GTRFR4, GTCPR4, GTCNR4 connected to D[31–16] connected to D[15–0] Capture Figure 5-50. Timers Super-Cascaded Mode Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-64 Freescale Semiconductor...
Page 273 When the device is in either mode, the PMC is capable of placing the device into one of the supported low-power states and supporting the power management event (PME) signaling protocol. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-65...
Page 274 0x00B0C Power management controller configuration register 1 (PMCCR1) 0x0000_0000 5.8.2.4/5-70 0x00B10 Power management controller configuration register 2 (PMCCR2) 0x0002_0002 5.8.2.5/5-72 0x00B14– Reserved — — — 0x00BFC MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-66 Freescale Semiconductor...
Page 275 1 The system will enter low power state when a quiesce request from the PowerPC core arrives. This bit is cleared when the device exits from low power state. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-67...
Page 276 (writing zero has no effect). Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-68 Freescale Semiconductor...
Page 277 If PMCMR[PMCIE] is set, the PMC interrupt request to the PowerPC core is driven, causing the PowerPC core to exit its low power state. PMCI can be cleared by writing a 1 to it (writing zero has no effect). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-69...
Page 278 PME (power management event) signaling, toggling of the external power switch, and indication of current and desired power states. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-70 Freescale Semiconductor...
Page 279 1 On transitions to D3 state, negate the EXT_PWR_CTRL signal to switch external power low (VDD = 0). On wake-up assert EXT_PWR_CTRL to switch VDD power on. — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-71...
Page 280 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Figure 5-55. Power Management Controller Configuration Register 2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-72 Freescale Semiconductor...
Page 281 Many blocks in the device can dynamically turn off clocks within the block when sections of the block are idle. This feature is always enabled and occurs automatically. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-73...
Page 282 This mode is referred to as D3Warm (described below). Figure 5-56 illustrates the power segmentation provided on the device. Sequencing in and out of D3Warm will be described in the following sections. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-74 Freescale Semiconductor...
Page 283 Default state; full power; PME signaling supported through software control e300 in Doze mode; e300 PLL running; PME signaling supported e300 in Nap state; e300 PLL running; PME signaling supported MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-75...
Page 284 PCI PME# (PCI_PME). • Properly sequencing the device into and out its lowest power mode where VDD is removed to a portion of the die. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-76 Freescale Semiconductor...
Page 285 Core is stopped with its clocks off. Core Active Negated PCIPMR1[P clocks powered down to all blocks (including owerState]= core time base) except to the interrupt unit. System operates normally. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-77...
Page 286 The power management controller then signals the core and acknowledges it’s request to enter power down mode. Finally the QUIESCE output signal is asserted. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-78 Freescale Semiconductor...
Page 287 Software is required to enable PMCI interrupt by setting PMCMR[PMCIE], otherwise exiting from low power state is not possible. NOTE It is the software’s responsibility to clear PMCER[PMCI]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-79...
Page 288 In this case, the PMC will assert an interrupt to the e300 core, but this action will not set any of the wake-up events in the PMC event register (PMCER). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-80 Freescale Semiconductor...
Page 289 (see Case 2). Other (e.g., e300 Same as D1 state (Case 6), except e300 transitions to Full On mode decrementer timer, from Nap state. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-81...
Page 290 PCI (PME input). Since the device is the host, PME signaling refers to external agents asserting the PCI_PME input to the device, which is one of the defined wake-up events. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-82 Freescale Semiconductor...
Page 291 D0 state into the PCI configuration registers (PCIPMR1[Power_State] = 00. This action will cause an interrupt to the e300 (D1–D3Hot) or cause the PMC to begin the wake-up process (D3Warm). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-83...
Page 292 PMC Power-Down When the MPC8313E is a PCI Agent In this case the PCI device driver runs on an external PCI host. It interfaces to the device through PCI configuration interface. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-84 Freescale Semiconductor...
Page 293 D3. This next_state change only generates an interrupt to the e300. the e300 will then sequence the device into the requested low power mode. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-85...
Page 294 4. The device detects the external agent’s PowerState change by polling the agent’s configuration registers. This process is repeated until all external agents are in their low power states. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-86 Freescale Semiconductor...
Page 295 PCIPMR1[Power_State] in the device PCI PME context block to “00” (D0). This change will be reflected in the PMCCR1[NEXT_STATE] register bits in the PMC module. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-87...
Page 296 12. The PMCCR1[CURR_STATE] register field is updated to reflect the new active state. This update is reflected in the PCIPMR1[Power_State] field indicating to the PCI host that the device has returned to its active state. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-88 Freescale Semiconductor...
Page 297 Figure 5-58 Figure 5-59. The use of the PMCCR2[RCNT] and PMCCR2[PDCNT] timer fields will allow calibration of the device to the switching characteristics of the power switch. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-89...
Page 298 VDDC VDDAC EXT_PWR_CTRL VDD VDDA External Host PCI_PME PCI_PME MPC8313E Host GPIO VAUX Control Figure 5-59. Example VDD Control of Device as Host MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-90 Freescale Semiconductor...
Page 299 This is mainly to prevent PMC from waking up in Host mode if there are inadvertent changes made to the PCIPMCR1[Power_State] register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-91...
Page 300 If the device is required to operate with the core permanently disabled, the following steps must be taken: 1. Initialize the device with the core enable. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-92 Freescale Semiconductor...
Page 301 By following this flow, the e300 core remains in low power state while the rest of the system is operational, and does not get out of this state as a result of any interrupt or time-based event. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 5-93...
Page 302 System Configuration MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 5-94 Freescale Semiconductor...
Page 303 Maximum number of consecutive transactions can be limited by programming arbiter configuration register. See Section 6.2.1, “Arbiter Configuration Register (ACR),” for more details. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 304 Note that the reset value of COREDIS and bits 10–11 are determined from reset configuration word. (See Section 4.3.2, “Reset Configuration Words,” for more details on reset configuration word.) Figure 6-1. Arbiter Configuration Register (ACR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 305 111 8 consecutive transactions Note: It is recommended not to program this field for more than four consecutive transactions. 24–25 — Reserved, write should preserve reset value. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 306 When ATO = n, the timeout cycle is n*128. 0000 Reserved 0001 128 clock cycles 0002 256 clock cycles 0003 384 clock cycles FFFF 8355840 clock cycles MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 307 1 Data time out timer is expired. Address time out. Reports on address tenure time out. 0 Address time out timer is not expired. 1 Address time out timer is expired. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 308 1 Data tenure time out causes MCP interrupt. Address time out. Address tenure time out interrupt definition. 0 Address tenure time out causes regular interrupt. 1 Address tenure time out causes MCP interrupt. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 309 Refer to Section 6.4.2, “Error Handling Sequence,” for more information. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 310 010 32 bytes 100 4 bytes 011–111 Reserved 101 5 bytes 110 6 bytes 111 7 bytes 000 8 bytes 24–26 — Write reserved, read = 0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 311 Table 6-8. AEADR Field Descriptions Bits Name Description 0–31 ADDR Address of the event reported in AEATR register. See Section 6.2.6, “Arbiter Event Attributes Register (AEATR),” for more information. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 312 The arbitration process involves the masters and the arbiter. Masters arbitrate on the privilege to own an address tenure. For data tenures, the arbiter uses the same order of transactions as address tenures. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 6-10 Freescale Semiconductor...
Page 313 • M6 gets 1/2 of the bus bandwidth • M4 and M5 each gets 1/6 of the bus bandwidth MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 6-11...
Page 314 See Section 3.2.5, “Transaction Ordering and Posting,” of the PCI Local Bus Specifications Rev 2.2, for more information. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 6-12 Freescale Semiconductor...
Page 315 (programmed by ATR[ATO]). In this case, the arbiter performs as follows: 1. Ends the address tenure. 2. Starts data tenure and ends it by asserting transfer error. 3. Reports on the event to AER[ATO]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 6-13...
Page 316 AO transaction in this system, the bus monitor allows the detection of AO transactions and treats them as an error. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 6-14 Freescale Semiconductor...
Page 317 4. Issues reset request, MCP or regular interrupt according to AERR[ECW] and AIDR[ECW], if enabled by AMR[ECW]. 5. Updates transaction attributes and address of AEATR and AEADR for the first error event. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 6-15...
Page 318 Use HRESET to reset the chip to guarantee that the information stored in AEATR and AEADR is not lost. 3. Clear all the previous events by writing ones to the AER. This register is also cleared after reset. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 6-16 Freescale Semiconductor...
Page 319 Figure 7-1 shows a block diagram of the e300c3 core. Note that the e300c3 supports floating-point operations and includes two integer units. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 320 I Cache Debug/COP PLL & Clock JTAG Interface Multiplier Touch Load Buffer Core Interface Copy-Back Buffer 32-Bit Address Bus 64-Bit Data Bus Figure 7-1. e300c3 Core Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 321 — As many as five instructions in execution per clock — Single-cycle execution for most instructions — Pipelined floating-point unit (FPU) for all single- and double-precision operations MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 322 — True little-endian mode for compatibility with other true little-endian devices — Critical interrupt support — Hardware support for misaligned little-endian accesses — Configurable processor bus frequency multipliers as defined in the MPC8313E Integrated Processor Hardware Specifications MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 323 The pm_event_in input signal can be used by the performance monitor counters to trigger an interrupt upon overflow on the e300c3 . • Bus clock—PLL configuration signals include seven signals for settings and control: pll_cfg[0:6]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 324 For a more detailed overview of instruction dispatch, see Section 7.3.6, “Instruction Timing.” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 325 The e300c3 core supports all floating-point data types based on the IEEE 754 standard (normalized, denormalized, NaN, zero, and infinity) in hardware, eliminating the latency incurred by software interrupt routines. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 326 The core provides separate instruction and data caches and MMUs. The core also provides an efficient processor bus interface to facilitate access to main memory and other bus subsystems. The memory subsystem support functions are described in the following sections. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 327 GPRs. Shadow registers are used only for servicing a TLB miss. Section 7.3.5.2, “Implementation-Specific Memory Management,” for more information about memory management for the core. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 328 (for example, allowing a snoop push to be enveloped by the address and data MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-10 Freescale Semiconductor...
Page 329 The contents of the decrementer register are decremented once every four bus clock cycles, and the decrementer interrupt is generated as the count passes through zero. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-11...
Page 330 — The performance monitor global control register (PMGC0) controls the counting of performance monitor events. It takes priority over all other performance monitor control registers. UPMGC0 provides user-level read access to PMGC0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-12 Freescale Semiconductor...
Page 331 Section 7.3.5, “Memory Management,” describes generally the conventions for memory management among these cores. This section also describes the core implementation of the 32-bit PowerPC memory management specification. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-13...
Page 332 The numbers to the right of the SPRs indicate the number that is used in the syntax of the instruction operands for the move to/from SPR instructions. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-14 Freescale Semiconductor...
Page 333 PMR 128-131 UPMLCas PMCs PMR 16-19 PMLCas PMR 144-147 These registers are e300 core implementation-specific (not defined by the PowerPC architecture). Figure 7-2. e300 Programming Model—Registers MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-15...
Page 334 XER register—The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-16 Freescale Semiconductor...
Page 335 1 The processor is enabled to take an external interrupt, system management interrupt, or decrementer interrupt. Privilege level 0 The processor can execute both user- and supervisor-level instructions 1 The processor can only execute user-level instructions MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-17...
Page 336 Little-endian mode enable 0 The processor runs in big-endian mode 1 The processor runs in little-endian mode. All reserved bits should be set to zero for future compatibility. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-18 Freescale Semiconductor...
Page 337 DBAT and eight pairs of IBAT registers. See Figure 7-2 for a list of the SPR numbers for the BAT arrays. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-19...
Page 338 0 Disables instruction and data cache parity error reporting 1 Allows a detected cache parity error to cause a machine check interrupt if MSR[ME] = 1 or a checkstop if MSR[ME] = 0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-20 Freescale Semiconductor...
Page 339 For those transactions, however, ci reflects the state of the I bit in the MMU for that page regardless of cache disabled status. ICE is zero at power-up. 1 The instruction cache is enabled MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-21...
Page 340 0 M bit not reflected on bus for instruction fetches. Instruction fetches are treated as nonglobal on the bus. 1 Instruction fetches reflect the M bit from the WIM settings MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-22 Freescale Semiconductor...
Page 341 PLL configuration bit 1 (read-only) PLL configuration bit 2 (read-only) PLL configuration bit 3 (read-only) PLL configuration bit 4 (read-only) PLL configuration bit 5 (read-only) PLL configuration bit 6 (read-only) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-23...
Page 342 High BAT enable. Regardless of the setting of HID2[HBE], these BATs are accessible by mfspr and mtspr. 0 IBAT[4–7] and DBAT[4–7] are disabled 1 IBAT[4–7] and DBAT[4–7] are enabled 14–15 — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-24 Freescale Semiconductor...
Page 343 110 way 0 through way 2 locked in e300c3. 111 way 0 through way 2 locked in e300c3. Setting HID0[DLOCK] will lock all ways. 27–31 — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-25...
Page 344 TLBs, and the segment registers. — Move to/from SPR instructions — Move to/from MSR — Move to/from PMR — Synchronize — Instruction synchronize MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-26 Freescale Semiconductor...
Page 345 The core implements the following instruction which is added to support critical interrupts (also supported on the G2_LE). This is a supervisor-level, context synchronizing instruction. — Return from Critical Interrupt (rfci) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-27...
Page 346 A fast hardware invalidation capability is provided to support cache maintenance. The e300c3 data cache is configured as 128 sets of four blocks per set. The organization of the data cache is shown in Figure 7-3. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-28 Freescale Semiconductor...
Page 347 The snoop access is given first access to the tags. The load or store then occurs on the clock following the snoop. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-29...
Page 348 To prevent the program state from being lost due to a system reset, a machine check interrupt, or an instruction-caused interrupt in the interrupt handler, interrupt handlers should save the information stored in SRR0 and SRR1 early and before enabling external interrupts. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-30 Freescale Semiconductor...
Page 349 Note that Table 7-6 includes no synchronous, imprecise instructions. While the PowerPC architecture supports imprecise handling of floating-point exceptions, the core implements floating-point exception modes as precise. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-31...
Page 350 • The instruction is lswi, lswx, stswi, stswx, and the core is in little-endian mode. Note that PowerPC little-endian mode is not supported on the e300 core. • The operand of dcbz is in memory that is write-through-required or caching-inhibited. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-32 Freescale Semiconductor...
Page 351 Occurs when the address (bits 0–29) in the IABR matches the next instruction to complete address in the completion unit, and IABR[30] is set. Note that the e300 core also implements breakpoint IABR2, which functions identically to IABR. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-33...
Page 352 Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the most recently used page table MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-34 Freescale Semiconductor...
Page 353 FPU, allowing up to three instructions to execute in the FPU concurrently. The FPU pipeline stages are multiply, add, and round-convert. The LSU has two MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-35...
Page 354 Test and control signals provide diagnostics for selected internal circuits. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-36 Freescale Semiconductor...
Page 355 ), checkstop signals, performance monitor signal (pm_event_in) via the PM counters, and both soft reset and hard reset signals. They are used to interrupt and, under various conditions, to reset the core. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-37...
Page 356 The ext_halt input pin can be used to force the core into halted state. The halted state may be a hardstop, conditional upon the HARDSTOP condition being set through the JTAG/debug interface MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-38 Freescale Semiconductor...
Page 357 Instruction cache way — The e300 core can protect locked ways in the instruction cache protection from invalidation; the G2_LE does not support instruction cache way protection. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 7-39...
Page 358 These are optional instructions in the PowerPC architecture. Reduced pin mode removed Reduced pin mode available Reduced pinout mode and the signal redpinmode will not be supported in the e300 core. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 7-40 Freescale Semiconductor...
Page 359 Software watchdog timer (WDT) • C controllers (I C1 and I • SPI controller (SPI) • Power management controller (PMC) • General-purpose I/O controller (GPIO) • External pins (IRQ[0:4]) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 360 (SIVCR, SCVCR, or SMVCR). In response to this read, the IPIC unit returns the vector (associated with the interrupt source) to the interrupt handler routine. In addition, the handler can vectorize different branches of interrupt handling. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 361 System Bus Arbiter Global Timers 1 Controller Global Timers 2 DDR SDRAM Controller GPIO Enhanced Local Bus Controller IRQ[0:4] Security Engine Figure 8-1. Interrupt Sources Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 362 IPIC; the interrupts are sent to the PowerPC core. The DMA controller can optionally (depending on the programming of the DMA registers) steer its interrupt to the PCI host through the PCI_INTA signal. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 363 Negated—There is no incoming interrupt from that source. Timing Assertion—All of these inputs can be asserted completely asynchronously. Negation—Interrupts programmed as level-sensitive must remain asserted until serviced. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 364 System internal interrupt pending register (SIPNR_L) 0x0000_0000 8.5.3/8-11 0x10 System internal interrupt group A priority register (SIPRR_A) 0x0530_9770 8.5.4/8-13 0x1C System internal interrupt group D priority register (SIPRR_D) 0x0530_9770 8.5.5/8-14 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 365 — MPSB MPSA — IPSD IPSC IPSB IPSA — HPIT — Reset All zeros Figure 8-2. System Global Interrupt Configuration Register (SICFR) Table 8-4 defines the bit fields of SICFR. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 366 01 smi request is asserted to the core for HPI. 10 cint request is asserted to the core for HPI. 11 Reserved. 24–31 — Write ignored, read = 0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 367 Interrupt ID Number Interrupt Meaning Interrupt Vector Error (no interrupt) 0b000_0000 1–8 Reserved 0b000_0001–0b000_1000 UART1 0b000_1001 UART2 0b000_1010 0b000_1011 eTSEC1 1588 timer 0b000_1100 eTSEC2 1588 timer 0b000_1101 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 368 0b100_0000 0b100_0001 0b100_0010 Reserved 0b100_0011 RTC ALR 0b100_0100 0b100_0101 0b100_0110 0b100_0111 GTM4 0b100_1000 GTM8 0b100_1001 GPIO 0b100_1010 Reserved 0b100_1011 0b100_1100 0b100_1101 GTM2 0b100_1110 GTM6 0b100_1111 0b101_0000 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-10 Freescale Semiconductor...
Page 369 SIMSR_H. Table 8-7. SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments Bits Field TSEC1 Tx TSEC1 Rx TSEC1 Err TSEC2 Tx TSEC2 Rx TSEC2 Err USB DR 7–23 — UART1 UART2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-11...
Page 370 SIPNR_L fields. Note that these field assignments are also valid for SIFCR_L and SIMSR_L. Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments Bits Field RTC SEC — RTC ALR GTM4 GTM8 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-12 Freescale Semiconductor...
Page 371 Tx), TSEC2 receive request (TSEC2 Rx) TSEC2 transmit/receive error (TSEC2 Err), USB DR, internal interrupt signals. For more information, see Section 8.6.3, “Internal Interrupts Group Relative Priority.” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-13...
Page 372 24 25 27 28 SYSD0P SYSD1P SYSD2P SYSD3P SYSD4P SYSD5P SYSD6P SYSD7P — — Reset 0 Figure 8-7. System Internal Interrupt Group D Priority Register (SIPRR_D) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-14 Freescale Semiconductor...
Page 373 Offset 0x20 Access: Read/write n (Implemented bits are listed in Table 8-7.) Reset All zeros Figure 8-8. System Internal Interrupt Mask Register (SIMSR_H) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-15...
Page 374 8-10, defines the IPIC output interrupt type (int, cint, or smi) in the SYSA0–SYSA1 and SYSD0–SYSD1 priority positions. All other priority positions assert int to the core. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-16 Freescale Semiconductor...
Page 375 10 cint request is asserted to the core for SYSA0. 11 Reserved. 26–27 SYSA1T Same as SYSA0T, but for SYSA1T 28–31 — Write ignored, read = 0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-17...
Page 376 24 25 27 28 MIXA0P MIXA1P MIXA2P MIXA3P — MIXA4P MIXA5P MIXA6P MIXA7P — Reset 0 Figure 8-12. System Mixed Interrupt Group A Priority Register (SMPRR_A) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-18 Freescale Semiconductor...
Page 377 24 25 27 28 MIXB0P MIXB1P MIXB2P MIXB3P — MIXB4P MIXB5P MIXB6P MIXB7P — Reset 0 Figure 8-13. System Mixed Interrupt Group B Priority Register (SMPRR_B) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-19...
Page 378 This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0) The user should drive all IRQ inputs to an inactive state prior to reset negation Figure 8-14. System External Interrupt Mask Register (SEMSR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-20 Freescale Semiconductor...
Page 379 MIXA0T MIXA1T — Reset All zeros EDI0 EDI1 EDI2 EDI3 EDI4 EDI5 EDI6 EDI7 — Reset All zeros Figure 8-15. System External Interrupt Control Register (SECNR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-21...
Page 380 SERSR bit. Offset 0x40 Access: Read/write INT n (Implemented bits are listed in Table 8-21) Reset All zeros Figure 8-16. System Error Status Register (SERSR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-22 Freescale Semiconductor...
Page 381 SERMR bit although no MCP request is passed to the core in this case. The SERMR can be read by the user at any time. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-23...
Page 382 MCP route. Route MCP request to either MCP_OUT or PCI_INTA (in core disable mode). 0 MCP routed to PCI_INTA (in core disable mode). 1 MCP routed to MCP_OUT (in core disable mode). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-24 Freescale Semiconductor...
Page 383 SIFCR x bit. SIFCR x bit positions are not changed according to their relative priority. Writes to unimplemented (reserved) bits are ignored; read = 0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-25...
Page 384 SERSR bit). The SERFR can be read by the user at any time. Offset 0x5C Access: Read/write INT n (Implemented bits are listed in Table 8-21.) Reset All zeros Figure 8-22. System Error Status Register (SERFR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-26 Freescale Semiconductor...
Page 385 System Management Interrupt Vector Register (SMVCR) SMVCR, shown in Figure 8-24, contains a 7-bit code (Table 8-30) representing the unmasked system management interrupt (SMI) source of the highest priority level. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-27...
Page 386 IPIC, informing the processor of error conditions, assertion of the external MCP request, and other conditions. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-28 Freescale Semiconductor...
Page 387 PowerPC core until software can handle them. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-29...
Page 388 Spread. In the spread scheme, priorities are spread over the table so other sources can have lower interrupt latencies. This scheme is also programmed but cannot be changed dynamically. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-30 Freescale Semiconductor...
Page 389 MIXB1 (Grouped) MIXB2 (Grouped) MIXB3 (Grouped) MIXB1 (Spread) SYSA0 (Grouped) SYSA1 (Grouped) SYSA2 (Grouped) SYSA3 (Grouped) MIXA2 (Spread) SYSA4 (Grouped) SYSA5 (Grouped) SYSA6 (Grouped) SYSA7 (Grouped) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-31...
Page 390 SYSD4 (Grouped) SYSD5 (Grouped) SYSD6 (Grouped) SYSD7 (Grouped) MIXB4 (Spread) GTM4 Reserved SYSA0 (Spread) GTM8 Reserved SYSD0 (Spread) Reserved GPIO MIXA5 (Spread) Reserved Reserved SYSA1 (Spread) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-32 Freescale Semiconductor...
Page 391 SYSA3 (Spread) Reserved Reserved SYSD3 (Spread) Reserved Reserved MIXB6 (Spread) GTM3 Reserved SYSA4 (Spread) GTM7 Reserved SYSD4 (Spread) Reserved Reserved MIXA7 (Spread) Reserved Reserved SYSA5 (Spread) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-33...
Page 392 When an interrupt source has multiple interrupting events, the user can individually mask these events by programming a mask register within that particular block. Table 8-31 shows which interrupt sources have multiple interrupting events. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-34 Freescale Semiconductor...
Page 393 The PIC supports the non-maskable machine check interrupts. When an error interrupt signal is received, the interrupt controller indicates the source by setting the corresponding SERSR bit. These sources are listed in Table 8-21. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 8-35...
Page 394 Integrated Programmable Interrupt Controller (IPIC) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 8-36 Freescale Semiconductor...
Page 395 ‘logical bank’ refers to one of the four or eight sub-banks in each SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address (MBA) pins during a memory access. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 396 — Unbuffered and registered DRAM modules • Open page management (dedicated entry for each logical bank) • Automatic DRAM initialization sequence or software-controlled initialization sequence • Automatic DRAM data initialization MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 397 All zeros MCAS Column address strobe MA[14:0] Address bus All zeros MBA[2:0] Logical bank address All zeros MCS[0:1] Chip selects All ones Write enable MRAS Row address strobe MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 398 A8 (alternate AP for DDR) MBA2 MBA2 MBA1 MBA1 MBA0 MBA0 Auto-precharge for DDR signaled on A10 when DDR_SDRAM_CFG[PCHB8] = 0. Auto-precharge for DDR signaled on A8 when DDR_SDRAM_CFG[PCHB8] = 1. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 399 TIMING_CFG_1[CASLAT] to be m clocks, data strobes at the DRAM assert coincident with the data on clock edge n + m . See the JEDEC DDR SDRAM specification for more information. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 400 Section 9.4.1.6, “DDR SDRAM Timing Configuration 2 (TIMING_CFG_2),” and Section 9.4.1.3, “DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).” High impedance—MRAS is always driven unless the memory controller is disabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 401 Meaning clocks. A clock edge is seen by the SDRAM when the true and complement cross. Timing Assertion/Negation—Timing is controlled by the DDR_CLK_CNTL register at offset 0x130. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 402 TIMING_CFG_3—DDR SDRAM timing configuration 3 0x0000_0000 9.4.1.3/9-11 0x104 TIMING_CFG_0—DDR SDRAM timing configuration 0 0x0011_0105 9.4.1.4/9-12 0x108 TIMING_CFG_1—DDR SDRAM timing configuration 1 0x0000_0000 9.4.1.5/9-14 0x10C TIMING_CFG_2—DDR SDRAM timing configuration 2 0x0000_0000 9.4.1.6/9-16 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 403 Offset 0x000, 0x008 Access: Read/Write 15 16 23 24 — SA n — EA n Reset All zeros Figure 9-2. Chip Select Bounds Registers (CS n _BNDS) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor...
Page 404 Chip select n enable 0 Chip select n is not active 1 Chip select n is active and assumes the state set in CS n _BNDS. 1–7 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-10 Freescale Semiconductor...
Page 405 DDR SDRAM timing configuration register 3, shown in Figure 9-4, sets the extended refresh recovery time, which is combined with TIMING_CFG_1[REFREC] to determine the full refresh recovery time. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-11...
Page 406 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Figure 9-5. DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-12 Freescale Semiconductor...
Page 407 000 Reserved 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-13...
Page 408 Figure 9-6. DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) Table 9-10 describes TIMING_CFG_1 fields. Table 9-10. TIMING_CFG_1 Field Descriptions Bits Name Description — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-14 Freescale Semiconductor...
Page 409 1011 6 clocks 0100 2.5 clocks 1100 6.5 clocks 0101 3 clocks 1101 7 clocks 0110 3.5 clocks 1110 7.5 clocks 0111 4 clocks 1111 8 clocks MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-15...
Page 410 21 22 23 25 26 — ADD_LAT — WR_LAT — RD_TO_PRE WR_DATA_DELAY — CKE_PLS FOUR_ACT Reset All zeros Figure 9-7. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-16 Freescale Semiconductor...
Page 411 010; for DDR1 with burst length of 8, must be set to 100. 000 Reserved 100 4 cycles 001 1 cycle 101–111 Reserved 010 2 cycles 011 3 cycles MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-17...
Page 412 DYN_PWR 8_BE NCAP — Reset 24 25 2T_EN BA_INTLV_CTL — x32_EN PCHB8 HSE — MEM_HALT Reset All zeros Figure 9-8. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-18 Freescale Semiconductor...
Page 413 If one of these devices is used, then this bit needs to be set if auto precharge is used. 0 DRAMs in system support concurrent auto-precharge. 1 DRAMs in system do not support concurrent auto-precharge. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-19...
Page 414 DDR_SDRAM_CFG[DLL_RST_DIS]. If a DLL reset is required, then the controller should be forced to enter and exit self refresh after the controller is enabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-20 Freescale Semiconductor...
Page 415 01 Assert ODT to internal IOs only during writes to DRAM 10 Assert ODT to internal IOs only during reads to DRAM 11 Always keep ODT asserted to internal IOs 11–15 — Reserved. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-21...
Page 416 9-10, sets the values loaded into the DDR’s mode registers. Offset 0x118 Access: Read/Write 15 16 ESDMODE SDMODE Reset All zeros Figure 9-10. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-22 Freescale Semiconductor...
Page 417 ESDMODE3, which, in the big-endian convention shown in Figure 9-11, corresponds to ESDMODE3[15]. The msb of the SDRAM extended mode 3 register value must be stored at ESDMODE3[0]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-23...
Page 418 Select chip select. Specifies the chip select that is driven active due to any command forced by software in DDR_SDRAM_MD_CNTL. 00 Chip select 0 is active 01 Chip select 1 is active 10 Reserved 11 Reserved — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-24 Freescale Semiconductor...
Page 419 DDR_SDRAM_MD_CNTL fields should be set for each of the tasks described above. Table 9-17. Settings of DDR_SDRAM_MD_CNTL Fields Clock Enable Signals Field Mode Register Set Refresh Precharge Control MD_EN — SET_REF — SET_PRE — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-25...
Page 420 If BSTOPRE is zero, the DDR memory controller uses auto-precharge read and write commands rather than operating in page mode. This is called global auto-precharge mode. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-26 Freescale Semiconductor...
Page 421 Clock is launched 3/4 applied cycle after address/command Clock is launched 1 applied cycle after address/command 101–111 Reserved — Reserved, should be cleared. 9–31 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-27...
Page 422 IP block ID. For the DDR controller, this value is 0x0002. 16–23 IP_MJ Major revision. This is currently set to 0x02. 24–31 IP_MN Minor revision. This is currently set to 0x01. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-28 Freescale Semiconductor...
Page 423 Programmable parameters allow for a variety of memory organizations and timings. The controller allows as many as 16 pages to be open simultaneously. The amount of time (in clock cycles) the pages remain open is programmable with DDR_SDRAM_INTERVAL[BSTOPRE]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-29...
Page 424 This delay is implemented in the controller for both reads and writes. The address and command interface is also source synchronous, although 1/4 cycle adjustments are provided for adjusting the clock alignment. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-30 Freescale Semiconductor...
Page 425 The DDR memory controller drives 15 address pins, but in this example the DDR SDRAM devices use only 12 bits. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-31...
Page 426 The data path to individual physical banks is bits wide. The DDR memory controller supports physical bank sizes from 16 Mbytes to 512 Mbytes. The physical banks can MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-32 Freescale Semiconductor...
Page 427 32 Mbits x 16 13 x 10 x 2 128 Mbytes 256 Mbytes 1 Gbits 128 Mbits x 8 14 x 11 x 2 512 Mbytes 1 Gbyte MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-33...
Page 428 MA[14:0] use MA[14] as the msb and MA[0] as the lsb. Also, MA[10] is used as the auto-precharge bit in DDR1/DDR2 modes for reads and writes, so the column address can never use MA[10]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-34 Freescale Semiconductor...
Page 429 11 10 9 10 x 2 MCAS 12 x MRAS 11 10 9 9 x 2 MCAS 12 x MRAS 11 10 9 8 x 2 MCAS MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-35...
Page 430 MRAS 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-36 Freescale Semiconductor...
Page 431 During each succeeding clock edge, additional data is transferred to the sense amplifiers from the data pins without additional write commands. The MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-37...
Page 432 Column auto-precharge Write Logical bank select Column Write with Logical bank select Column auto-precharge Mode register set Opcode Opcode Opcode and mode Auto refresh Self refresh MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-38 Freescale Semiconductor...
Page 433 125% of a cycle, from the registration of a write command. This parameter is not defined in the SDRAM specification. It is implementation-specific, defined for the DDR memory controller in TIMING_CFG_2. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-39...
Page 434 MRAS MCAS MA n CASLAT MDQ n D1 D2 D3 D1 D2 MDQS Figure 9-23. DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-40 Freescale Semiconductor...
Page 435 MA n MDQ[0:63] D1 D2 D3 D1 D2 D1 D2 D3 D1 D2 MDQS MDM[0:7] Figure 9-25. DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-41...
Page 436 SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles. SDRAM Clock MRAS MCAS MA n Code Code MBA n MDQ n MDQS Figure 9-27. DDR SDRAM Mode-Set Command Timing MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-42 Freescale Semiconductor...
Page 437 SDRAM clock cycle after the command is launched. The delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-43...
Page 438 3. Issues one or more auto-refresh commands to each DDR SDRAM bank (as identified by its chip select) to refresh one row in each logical bank of the selected physical bank. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-44 Freescale Semiconductor...
Page 439 DDR memory controller can be configured to take advantage of self-refreshing SDRAMs or to provide no refresh support. Self-refresh support is enabled with the SREN memory control parameter. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-45...
Page 440 TIMING_CFG_0[ACT_PD_EXIT] and TIMING_CFG_0[PRE_PD_EXIT]. A penalty of 1 cycle is shown in Figure 9-31. Mem Bus Clock COMMAND Figure 9-31. DDR SDRAM Power-Down Mode MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-46 Freescale Semiconductor...
Page 441 Figure 9-32. DDR SDRAM Self-Refresh Entry Timing SDRAM Clock MCKE MRAS MCAS MA n (High Impedance) MDQ n MDQS 200 Cycles Figure 9-33. DDR SDRAM Self-Refresh Exit Timing MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-47...
Page 442 Also, better performance can be obtained using more banks, especially in systems which use many different channels. Page mode is disabled by clearing DDR_SDRAM_INTERVAL[BSTOPRE] or setting CSn_CONFIG[AP_nEN]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-48 Freescale Semiconductor...
Page 443 Control configuration SREN NCAP 9.4.1.7/9-18 RD_EN 2T_EN SDRAM_TYPE BA_INTLV_CTL DYN_PWR x32_EN 32_BE 8_BE DDR_SDRAM_CFG_2 Control configuration DQS_CFG NUM_PR 9.4.1.8/9-21 ODT_CFG D_INIT DDR_SDRAM_MODE Mode configuration ESDMODE 9.4.1.9/9-22 SDMODE MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-49...
Page 444 Should be set according to the specifications for 9.4.1.5/9-14 Timing the memory used (t DDR2 Should be set according to the specifications for the memory used (t MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-50 Freescale Semiconductor...
Page 445 Should be set to CAS latency – 1 cycle. For example, if the CAS latency if 5 cycles, then this field should be set to 100 (4 cycles). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-51...
Page 446 0s. DDR2 Can be set to any value, depending on the application. Auto precharge can be enabled by setting this field to all 0s. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-52 Freescale Semiconductor...
Page 447 If the bypass initialization mode is used, then software can initialize the memory through the DDR_SDRAM_MD_CNTL register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 9-53...
Page 448 DDR Memory Controller MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 9-54 Freescale Semiconductor...
Page 449 LWE[0:1] Local Address LA[0:25] LALE Address and LPBSE Local Data Data Machine LDVAL Transfer Acknowledge LSRCID[0:4] LAD[0:15] LCLK[0:1] Figure 10-1. Enhanced Local Bus Controller Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-1...
Page 450 — Read-only ECC registers to verify after write operation — Boot chip-select support for 8-bit devices — Dual 2-Kbyte/eight 512-byte buffers allow simultaneous data transfer during flash reads and programming MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-2 Freescale Semiconductor...
Page 451 UPM array words in UPM mode. The bus clock is driven identically onto pins, LCLK[0:1], to allow the clock load to be shared equally across a set of signal nets, thereby enhancing the edge rates of the bus clock. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-3...
Page 452 General purpose line 1 Reset_cfg LFALE LFALE Flash address latch enable LOE/ GPCM Output enable LGPL2/ LFRE Flash read enable LFRE LGPL2 General purpose line 2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-4 Freescale Semiconductor...
Page 453 LCS[0:3] are provided on a per-bank basis with LCS0 corresponding to the chip select for memory bank 0, which has the memory type and attributes defined by BR0 and OR0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-5...
Page 454 LGPL5 General-purpose line 5 State Asserted/Negated—One of six general purpose signals when in UPM mode, and drives a Meaning value programmed in the UPM array. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-6 Freescale Semiconductor...
Page 455 ID relating to the data transfer is indicated. In case of address debug, LSRCID[0:4] is valid only when the address on LAD consists of all physical address bits—with optional padding—for reconstructing the system address presented to the eLBC. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-7...
Page 456 0x0A0 LURT—UPM refresh timer 0x0000_0000 10.3.1.4/10-20 0x0A4– Reserved — — — 0x0AC 0x0B0 LTESR—Transfer error status register 0x0000_0000 10.3.1.9/10-25 0x0B4 LTEDR—Transfer error disable register 0x0000_0000 10.3.1.10/10-27 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-8 Freescale Semiconductor...
Page 457 Bits designated as write-one-to-clear are cleared only by writing ones to them. Writing zeros to them has no effect. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-9...
Page 458 LTESR[WP] is set (if WP is set) if a write to this memory bank is attempted, and a local bus error interrupt is generated (if enabled), terminating the cycle. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-10 Freescale Semiconductor...
Page 459 Boot Source OR0 Reset Value FCM (small page NAND Flash) 0000_03AE FCM (large page NAND Flash) 0000_07AE GPCM 0000_0FF7 eLBC not used as a boot source 0000_0F07 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-11...
Page 460 8 Mbytes 1111_1111_1100_0000_0 4 Mbytes 1111_1111_1110_0000_0 2 Mbytes 1111_1111_1111_0000_0 1 Mbyte 1111_1111_1111_1000_0 512 Kbytes 1111_1111_1111_1100_0 256 Kbytes 1111_1111_1111_1110_0 128 Kbytes 1111_1111_1111_1111_0 64 Kbytes 1111_1111_1111_1111_1 32 Kbytes MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-12 Freescale Semiconductor...
Page 461 LCS n and LWE are negated normally. LCS n and LWE are negated normally. 4 or 8 LCS n and LWE are negated one quarter bus clock cycle earlier. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-13...
Page 462 • Works in conjunction with EHTR to extend hold time on read accesses. • LCS n (only if ACS is not equal to 00) and LWE signals are negated one cycle earlier during writes. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-14 Freescale Semiconductor...
Page 463 Refer to Table 10-5 for the OR0 reset value. All other option registers have all bits cleared. Figure 10-4. Option Registers (OR ) in FCM Mode MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-15...
Page 464 The write-enable is asserted 0.5 clock cycles after any command, address, or data. The write-enable is asserted 1 clock cycle after any command, address, or data. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-16 Freescale Semiconductor...
Page 465 • Works in conjunction with CBT to extend the wait time for read/busy status sampling by 16 clock cycles. • Works in conjunction with EHTR to double hold time on read accesses. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-17...
Page 466 0 Corresponding address bits are masked. 1 The corresponding address bits are used in the comparison with address pins. 17–18 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-18 Freescale Semiconductor...
Page 467 Table 10-10. MAR Field Descriptions Bits Name Description 0–31 Address that can be output to the address signals under control of the AMX bits in the UPM RAM word. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-19...
Page 468 UWPL LUPWAIT polarity active low. Sets the polarity of the LUPWAIT pin when in UPM mode. 0 LUPWAIT is active high. 1 LUPWAIT is active low. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-20 Freescale Semiconductor...
Page 469 Read loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or single-beat read pattern or when M x MR[OP] = 11 ( command) 0000 16 0001 1 0010 2 0011 3 1110 14 1111 15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-21...
Page 470 RAM array for UPM read or write commands. MDR also contains data written to or read from an external NAND Flash EEPROM for FCM write address, write data, and read status commands. MDR MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-22 Freescale Semiconductor...
Page 471 The UPM and FCM have different indications of when such special operations are completed. The behavior of eLBC is unpredictable if special operation modes are altered between LSOR being written and the relevant memory controller completing that access. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-23...
Page 472 UPM. The qualified banks rotate their requests. Offset 0x0_50A0 Access: Read/Write LURT — Reset All zeros Figure 10-12. UPM Refresh Timer (LURT) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-24 Freescale Semiconductor...
Page 473 LTESR, LTEATR[V] must be cleared for LTESR to updated again. Offset 0x0_50B0 Access: w1c — — ATMW ATMR — — Reset All zeros — Reset All zeros Figure 10-13. Transfer Error Status Register (LTESR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-25...
Page 474 1 UPM Run pattern operation has completed, allowing software to continue processing of results. FCM command completion event 0 No FCM operation in progress, or operation pending. 1 FCM operation has completed, allowing software to continue processing of results. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-26 Freescale Semiconductor...
Page 475 1 RAWA error checking is disabled. 10–11 — Reserved Chip select error checking disable. 0 Chip select error checking is enabled. 1 Chip select error checking is disabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-27...
Page 476 1 FCM command time-out error reporting is enabled. PARI ECC error interrupt enable. 0 ECC error reporting is disabled. 1 ECC error reporting is enabled. 3–4 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-28 Freescale Semiconductor...
Page 477 Access: Read/Write 10 11 15 16 19 20 23 24 30 31 — — SRCID — Reset All zeros Figure 10-16. Transfer Error Attributes Register (LTEATR MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-29...
Page 478 10-18, is a write-1-to-clear register. Write operations can clear but not set bits. It captures the errors during full page read transfers on FCM command completion event, provided ECC check is enabled in BRx[DECC]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-30 Freescale Semiconductor...
Page 479 The local bus configuration register (LBCR) is shown in Figure 10-19. Offset 0x0_50D0 Access: Read/Write LDIS — BCTLC — Reset — BMTPS Reset All zeros Figure 10-19. Local Bus Configuration Register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-31...
Page 480 1001 PS = 4096 1010 PS = 8192 1011 PS = 16,384 1100 PS = 32,768 1101 PS = 65,536 1110 PS = 131,072 1111 PS = 262,144 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-32 Freescale Semiconductor...
Page 481 Once LCRR[CLKDIV] is written, the register should be read, and then an isync should be executed. 00000–00001 Reserved 00010 2 00011 Reserved 00100 4 00101–00111 Reserved 01000 8 01001–11111 Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-33...
Page 482 4-Kbyte boot block into the FCM buffer RAM, which maps only the 4 Kbytes of NAND flash main data region comprising the boot block. Any access to the buffer RAM is delayed until the entire boot block has been loaded. 21–22 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-34 Freescale Semiconductor...
Page 483 Software must not alter the contents of the addressed FCM buffer, FIR, MDR, FCR, FBAR, FPAR, or FBCR while an operation is in progress—or eLBC will behave unpredictably—but software can freely MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-35...
Page 484 NAND Flash device. Offset 0x0_50E8 Access: Read/Write 15 16 23 24 CMD0 CMD1 CMD2 CMD3 Reset All zeros Figure 10-23. Flash Command Register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-36 Freescale Semiconductor...
Page 485 NAND Flash page in both the external NAND Flash device and FCM buffer RAM. Offset 0x0_50F0 Access: Read/Write — Reset All zeros Figure 10-25. Flash Page Address Register, Small Page Device (ORx[PGS] = 0) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-37...
Page 486 The LSB of PI indexes one of the two 4 Kbyte buffers in the FCM buffer RAM as follows: 0 The page is transferred to/from FCM buffer 0, address offsets 0x0000–0x0FFF 1 The page is transferred to/from FCM buffer 1, address offsets 0x1000–0x1FFF MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-38 Freescale Semiconductor...
Page 487 It can be used for verify after write feature in software. Note that the valid bit sets before the command completion event and hence, the correct ECC could be read before actual completion of writes/reads. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-39...
Page 488 These patterns define how the external control signals behave during a read, write, burst-read, or burst-write access. Refresh timers are also available to periodically initiate user-defined refresh patterns. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-40 Freescale Semiconductor...
Page 489 (LAD pins). The LALE signal, when asserted, signifies an address phase during which the eLBC drives the memory address on the LAD pins. An external address MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-41...
Page 490 GPCM performing a 32-byte write starting at address 0x5420. Note that during each of the 32 assertions of LALE, LA[21:25] exactly mirror LAD[27:31], but during data phases, only LAD[0:7] is driven with valid data. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-42 Freescale Semiconductor...
Page 491 Note that TA and LALE are never asserted together, and that for the duration of LALE, LCSn (or any other control signal) remains negated or frozen. LCLK Address Data LALE LCS n Figure 10-31. Basic eLBC Bus Cycle with LALE, TA, and LCS n MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-43...
Page 492 UPM exception (as noted in Section 10.4.4.1.4, “Exception Requests,”) or terminate a GPCM access. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-44 Freescale Semiconductor...
Page 493 [ACS] to specify LCS to meet this requirement. Generally, the attributes for the memory cycle are taken from OR . These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR and SETA fields. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-45...
Page 494 Figure 10-34. GPCM General Read Timing Parameters Table 10-32 lists the signal timing parameters for a GPCM read access as the option register attributes are varied. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-46 Freescale Semiconductor...
Page 495 The write access cycle commences upon latching of the memory address (LALE negated), and concludes when LCSn returns high. LBCTL remains stable for the entire cycle to drive data onto any secondary data MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-47...
Page 496 1¾+SCY 2+SCY (½) (2+SCY) ½ 1½+SCY 2+SCY 2+SCY 2+SCY 1+SCY 2+SCY 1+SCY 3+SCY 2+SCY ¼ 2+SCY ¼ 1½+SCY 1¾+SCY (½) (1½+SCY) ½ 1¼+SCY 1¾+SCY (1+SCY) (1½+SCY) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-48 Freescale Semiconductor...
Page 497 One clock cycle later (for LCRR[CLKDIV] = 4), when OR [XACS] = 1. • Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when OR [XACS] = 1. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-49...
Page 498 When this attribute is asserted, the strobe is negated one quarter of a clock before the normal case provided that LCRR[CLDIV] = 4 or 8. For example, when ACS = 00 and MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-50 Freescale Semiconductor...
Page 499 LCRR[CLKDIV] = 2 for these examples is only to delay the assertion of LCSn in the ACS = 10 case to the ACS = 11 case. The example in Figure 10-38 also shows address and data multiplexing on LAD for a pair of writes issued consecutively. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-51...
Page 500 Figure 10-38. GPCM Relaxed Timing Back-to-Back Writes (XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-52 Freescale Semiconductor...
Page 501 LWE n Figure 10-40. GPCM Relaxed Timing Write (XACS = 0, ACS = 00, SCY = 1, CSNT = 1, TRLX = 1, CLKDIV = 4, 8) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-53...
Page 502 LALE Latched Address 1 Latched Address 2 LCS n LCSy LBCTL Figure 10-41. GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-54 Freescale Semiconductor...
Page 503 [SETA] = 1. The timing of LGTA is illustrated by the example in Figure 10-43. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-55...
Page 504 Table 10-34. Boot Bank Field Values after Reset for GPCM as Boot Controller Register Field Setting 0000_0000_0000_0000_0 From RCWH[ROMLOC] DECC MSEL ATOM MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-56 Freescale Semiconductor...
Page 505 ROM chip-select (LCS0) prior to the system being fully configured. 1. Note bit numbering reversal: LAD[0] (msb) connects to Flash IO[7], while LAD[7] (lsb) connects to IO[0]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-57...
Page 506 Figure 10-45. FCM Basic Page Read Timing (PGS = 1, CSCT = 0, CST = 0, CHT = 1, RST = 1, SCY = 0, TRLX = 0, EHTR = 1) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-58 Freescale Semiconductor...
Page 507 The FCM buffer space is divided into eight 1-Kbyte buffers for small-page devices (ORn[PGS] = 0), mapped as shown in Figure 10-46. Each page in a small-page NAND Flash comprises 528 bytes, where MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-59...
Page 508 FBCR[BC] = 0, FCM transfers an entire page, comprising the 2048-byte main region followed by the 64-byte spare region; the 1984-byte reserved region is not accessed, and remains undefined for MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-60 Freescale Semiconductor...
Page 509 510 byte 511 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Figure 10-48. FCM ECC Calculation MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-61...
Page 510 MDR all reset to select AS0 at the start of the instruction sequence. A complete list of op-codes can be found in Section 10.3.1.18, “Flash Instruction Register (FIR).” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-62 Freescale Semiconductor...
Page 511 The manufacturer’s datasheet should be consulted to determine values for programming into the FCR register, and whether a given command in the sequence is expected to initiate busy device behavior. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-63...
Page 512 (8-bit port size) of data into the next AS field of MDR. Reads beyond the fourth byte of MDR are discarded. The MDR read pointer is independent of the MDR write pointer used by UA and WS instructions. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-64 Freescale Semiconductor...
Page 513 Table 10-35. FCM Chip-Select to First Command Timing ORn[TRLX] ORn[CSCT] LCS n to First Command Delay 1 LCLK clock cycle 4 LCLK clock cycles 2 LCLK clock cycles 8 LCLK clock cycles MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-65...
Page 514 ½+2×SCY 3+2×SCY 8×(2+SCY) ½ 2×SCY ½+2×SCY 3+2×SCY 8×(2+SCY) 2×SCY 2×SCY 3+2×SCY 8×(2+SCY) In the parameters, SCY refers to a delay of OR n [SCY] clock cycles. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-66 Freescale Semiconductor...
Page 515 In addition, FCM samples and compares the state of LFRB on two consecutive cycles of LCLK to filter out noise on this signal as it rises to the ready state (LFRB = 1). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-67...
Page 516 = Read data cycle time. = Write to read turnaround time. Figure 10-55. FCM Read Data Timing (for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-68 Freescale Semiconductor...
Page 517 Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is the boot chip-select output; its operation differs from other external chip-select outputs after a system reset. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-69...
Page 518 4 Kbytes of contiguous, main region data, loaded from the first pages of the boot block, are accessible in eLBC bank 0, as indicated in Figure 10-57. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-70 Freescale Semiconductor...
Page 519 512-byte region is verified and single-bit errors are corrected if possible. If FCM is unable to correct ECC errors, eLBC halts the boot process and signals an unrecoverable error by asserting the hreset_req signal. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-71...
Page 520 A UPM refresh timer expires and requests a transaction, such as a DRAM refresh • A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an exception sequence MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-72 Freescale Semiconductor...
Page 521 Table 10-39. UPM Routines Start Addresses UPM Routine Routine Start Address Read single-beat (RSS) 0x00 Read burst (RBS) 0x08 Write single-beat (WSS) 0x18 Write burst (WBS) 0x20 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-73...
Page 522 MxMR[RFEN] bits are set. In this scenario, more than one chip select may assert at the same time, as refresh pattern runs for all banks assigned to UPM with RFEN bit set. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-74 Freescale Semiconductor...
Page 523 MR / MDR registers should not be updated while dummy read/write access is still in progress. If the MxMR[MAD] is incremented then the previous dummy transaction is already completed. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-75...
Page 524 Note that if step 1 (or 6) and 2 (or 7) are reversed, step 3 (or 8) is replaced by the following: • Read M MR to ensure that the M MR has already been updated with the desired configuration. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-76 Freescale Semiconductor...
Page 525 T1–T4, define four quarters of the bus clock cycle. Because T2 and T4 are inactive when LCRR[CLKDIV] = 2, UPM ignores signal timing programmed for assertion in either of these phases in the case LCRR[CLKDIV] = 2. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-77...
Page 526 External Signals Timing Generator BRn[PS], LA[24:25] Current Bank Byte Select CS Line Logic Selector LBS[0:1] LGPL0 LGPL1 LGPL2 LGPL3 LGPL4 LGPL5 LCS[0:3] Figure 10-63. RAM Array and Signal Generation MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-78 Freescale Semiconductor...
Page 527 Byte select timing 4. Defines the state (0 or 1) of LBS during bus clock quarter phase 4 (LCRR[CLKDIV] = 4 or 8), in conjunction with BR n [PS] and LA[24:25]. Ignored when LCRR[CLKDIV] = 2. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-79...
Page 528 G5T3 General purpose line 5 timing 3. Defines the state (0 or 1) of LGPL5 during bus clock quarter phases 3 and 4 (second half phase). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-80 Freescale Semiconductor...
Page 529 In case of UPM writes, program UTA and LAST in same RAM word. In case of UPM reads, program UTA and LAST in consecutive or same RAM words. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-81...
Page 530 Figure 10-65 shows how UPMs control LCSn signals. Bank Selected Switch LCS0 BR n [MSEL] UPMA/B/C LCS1 LCS2 LCS3 GPCM Figure 10-65. LCS n Signal Selection MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-82 Freescale Semiconductor...
Page 531 10-41. The next RAM word for which LOOP = 1 is recognized as a loop end word. When it is reached, the loop counter is decremented by one. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-83...
Page 532 (NA) bit of the RAM word is used to increment the current address. The effect of NA = 1 is visible only when AMX = 00 chooses the column address. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-84 Freescale Semiconductor...
Page 533 DLT3 bit in the same RAM word, in conjunction with M MR[GPL4], determines when the data input is sampled by the eLBC as follows: MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-85...
Page 534 LUPWAIT is negated. The value of external signals driven by the UPM remains as indicated in the previous RAM word. When LUPWAIT is negated, the UPM continues normal functions. Note that during WAIT cycles, the UPM does not handle data. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-86 Freescale Semiconductor...
Page 535 Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose some non-zero combination of OR [TRLX] and OR [EHTR]. The next accesses after a read access to the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-87...
Page 536 10-70. In non-multiplexed mode, waveforms etc remain the same except that few things need not be taken care of like ASHIFT parameter, LAD bus turnaround time, LALE timings etc. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-88 Freescale Semiconductor...
Page 537 This section is only a guideline, and the board designer must simulate the electric characteristics of the scenario to determine the maximum operating frequency. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-89...
Page 538 133-MHz bus frequency, LCS should arrive on the order of 3 bus clocks later. For data timings, only the propagation delay of one buffer plus the actual data setup time has to be considered. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-90 Freescale Semiconductor...
Page 539 (transceiver) time. The system designer has to ensure, that [t (LB) + t (transceiver)] is larger than t (LB) to avoid bus contention. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-91...
Page 540 Interface Output Register LAD[0:7] LAD[8:15] 16-Bit Port Size 8-Bit Port Size Figure 10-74. Interface to Different Port-Size Devices MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-92 Freescale Semiconductor...
Page 541 Throughout these examples it is assumed that one or more banks of eLBC has been configured under FCM control (BRn[MSEL] = 001), with base address, port size, ECC mode, and timing parameters configured in accordance with the device’s hardware specifications. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-93...
Page 542 4 bytes of ID during the sequence. The sequence is initiated by writing FMR[OP] = 10, and issuing a special operation to the bank. At the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-94 Freescale Semiconductor...
Page 543 OP2 = PA = page address; OP3 = CM1 = command 1; OP4 = RBW = wait on Flash ready and read data into FCM buffer; OP5–OP7 = NOP MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-95...
Page 544 NAND Flash device might already be driving it, contention will occur. In case OP5 and OP6 operations are skipped, it may also MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-96 Freescale Semiconductor...
Page 545 Here, LGPL1 is programmed to drive R/W of the DRAM, although any LGPL signal may be used for this purpose. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-97...
Page 546 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+1 RSS+2 Figure 10-75. Single-Beat Read Access to FPM DRAM MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-98 Freescale Semiconductor...
Page 547 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS+1 WSS+1 WSS+2 Figure 10-76. Single-Beat Write Access to FPM DRAM MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-99...
Page 548 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 Figure 10-77. Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-100 Freescale Semiconductor...
Page 549 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 Figure 10-78. Refresh Cycle (CBR) to FPM DRAM MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-101...
Page 550 The same interfacing is used for pipelined and flow-through versions of ZBT SRAMs. However different UPM patterns must be generated for those cases. Because ZBT MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-102 Freescale Semiconductor...
Page 551 (for read), and that the rest of the burst is ignored (by negating WE). The UPM controller basically has to wait for the end of the SRAM burst to avoid bus contention with further bus activities. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 10-103...
Page 552 RAM word, then the eLBC may not be able to sample the correct data during reads. Therefore, OE must be asserted earlier than TA. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 10-104 Freescale Semiconductor...
Page 553 I/O sequencer (IOS). Configuration Regs. I/F Configuration Regs. Power Management Buffer Pool I/O Sequencer (IOS) Figure 11-1. I/O Sequencer Block Diagram MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 11-1...
Page 554 POTAR5—PCI outbound translation address register 5 0x0000_0000 11.4.1/11-3 0x80 POBAR5—PCI outbound base address register 5 0x0000_0000 11.4.2/11-3 0x88 POCMR5—PCI outbound comparison mask register 5 0x0000_0000 11.4.3/11-4 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 11-2 Freescale Semiconductor...
Page 555 POBARn register fields. Offset 0x08, 0x20, 0x38, Access: Read/Write 0x50, 0x68, 0x80 11 12 — Reset All zeros Figure 11-3. PCI Outbound Base Address Registers (POBAR n ) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 11-3...
Page 556 I/O space. Determines whether the window is mapped to the PCI memory space or PCI I/O space. 0 Memory space 1 I/O space 2–11 — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 11-4 Freescale Semiconductor...
Page 557 0 Logic is active. 1 Logic is idle. There are no outstanding transactions in the IOS, the DMA, or the PCI port. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 11-5...
Page 558 Although the ports use a similar interface, the I/O sequencer is not actually symmetrical. The transaction forwarding from each source is explained in the following sections. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 11-6 Freescale Semiconductor...
Page 559 Transactions to these address ranges are issued on the PCI bus with a translated address. The translation addresses are defined in the associated PCI outbound translation address registers (POTARs). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 11-7...
Page 560 PCI port and were posted before the read data arrives from the PCI. • The IOS can always accept a write from the PCI port without forcing the PCI port to first accept a read. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 11-8 Freescale Semiconductor...
Page 561 Message and doorbell registers for inter-processor communication • DMA controller — Four DMA channels — Concurrent execution across multiple channels with programmable bandwidth control — Misaligned transfer capability MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-1...
Page 562 0x0000_0000 12.3.8.1/12-9 0x0_8204 DMASR2—DMA 2 status register 0x0000_0000 12.3.8.2/12-11 0x0_8208 DMACDAR2—DMA 2 current descriptor address register 0x0000_0000 12.3.8.3/12-12 0x0_8210 DMASAR2—DMA 2 source address register 0x0000_0000 12.3.8.4/12-13 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-2 Freescale Semiconductor...
Page 563 PCI bus. Figure 12-2 shows the OMISR fields. Offset 0x030 Access: Mixed OM1I OM0I — — Reset All zeros Figure 12-2. Outbound Message Interrupt Status Register (OMISR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-3...
Page 564 Table 12-3. OMIMR Field Descriptions Bits Name Description 31–4 — Reserved ODIM Outbound doorbell interrupt mask. 0 Outbound doorbell interrupt is allowed 1 Outbound doorbell interrupt is masked — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-4 Freescale Semiconductor...
Page 565 Table 12-5. OMR0 and OMR1 Field Descriptions Bits Name Description 31–0 OMSG n Outbound message n . Contains generic data to be passed between the local processor and external hosts. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-5...
Page 566 Write 1 from the PCI bus to clear. Writing 0 has no effect. (Writing a bit in this register from the CSB causes an interrupt (PCI_INTA) to be generated.) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-6 Freescale Semiconductor...
Page 567 Figure 12-8 shows the IMISR fields. Offset 0x080 Access: User Mixed MCI IDI IM1I — — Reset All zeros Figure 12-8. Inbound Message Interrupt Status Register (IMISR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-7...
Page 568 1 Machine check interrupt is masked. IMISR[MC1] is cleared IDIM Inbound doorbell interrupt mask. 0 Inbound doorbell interrupt is allowed 1 Inbound doorbell interrupt is masked. IMISR[IDI] is cleared. — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-8 Freescale Semiconductor...
Page 569 The BWC values are listed as follows: 000 1 cache line 001 2 cache lines 010 4 cache lines 011 8 cache lines 100 16 cache lines Others Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-9...
Page 570 DMA transfer. End-of-transfer is defined as the end of a direct mode transfer or in chaining mode, as the end of the transfer of the last segment of a chain. 0 No EOT interrupt is generated 1 EOT interrupt is generated 6–4 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-10 Freescale Semiconductor...
Page 571 Channel busy. This bit indicates whether the channel is busy. It is cleared as a result of any of the following conditions: an error or completion of the DMA transfer. 0 No DMA transfer is currently in progress 1 A DMA transfer is currently in progress MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-11...
Page 572 End-of-segment interrupt enable 0 No end-of-segment interrupt is generated. 1 An interrupt is generated when the current DMA transfer for the current descriptor is finished. 2–0 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-12 Freescale Semiconductor...
Page 573 Table 12-14 describes the DMADARn register. Table 12-14. DMASAR n Field Descriptions Bits Name Description 31–0 Destination address of DMA transfer.Updated after each DMA write operation. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-13...
Page 574 NEOSIE Next end-of-segment interrupt enable. 0 No end-of-segment interrupt is generated. 1 An interrupt is generated when the DMA transfer for the next descriptor is finished. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-14 Freescale Semiconductor...
Page 575 The interrupt to the local processor is cleared by writing 1 to the appropriate IMISR bit. The interrupt to PCI (PCI_INTA) is cleared by writing 1 to the appropriate OMISR bit. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-15...
Page 576 Direct mode, in direct mode, the DMA controller does not read a chain of descriptors from memory but instead uses the current parameters in the DMA registers to start a DMA transfer. The DMA MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-16 Freescale Semiconductor...
Page 577 (DMAMRn) or when encountering an error condition. In either case, the application software can do one of the following: • Continue the DMA transfer • Reconfigure the DMA for a new transfer MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-17...
Page 578 DMA transfer with the control parameters specified by the descriptor. The DMA controller traverses the descriptor chain until reaching the last descriptor (with its EOTD bit set). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-18 Freescale Semiconductor...
Page 579 If segment descriptors are written to memory located in the CSB, they should be treated like they are translated from big-endian to little-endian mode. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-19...
Page 580 The initialization steps of a DMA transfer in chaining mode are described as follows: 1. Build a chain of descriptor segments in memory. Refer to Section 12.4.4, “DMA Segment Descriptors.” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-20 Freescale Semiconductor...
Page 581 4. Initialize the DMAMRn[CTM] to indicate chaining mode. Other control parameters in the mode register can also be initialized here if necessary. 5. First clear then set the DMAMRn[CS] to start the DMA transfer. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 12-21...
Page 582 DMA/Messaging Unit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 12-22 Freescale Semiconductor...
Page 583 The PCI controller acts as a bridge between the PCI interface and the CSB. The I/O sequencer buffers the data. Figure 13-1 is a high-level block diagram of the PCI controller. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-1...
Page 584 Systems must not rely on inbound reads to ensure all pending outbound writes have completed. For example, consider the case where a core writes data to a PCI device and then updates a flag in the local MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-2 Freescale Semiconductor...
Page 585 When the device powers up in agent mode, it acknowledges inbound configuration accesses. Note that in PCI agent mode, the PCI controller ignores all PCI memory accesses except those to the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-3...
Page 586 PCI system error High impedance Required PCI_STOP PCI stop High impedance Required PCI_TRDY PCI target ready High impedance Required PCI_PME PCI PME assertion request High impedance Required MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-4 Freescale Semiconductor...
Page 587 State Asserted—The PCI interface signals use the 66-MHz PCI AC timing parameters. Meaning Negated—The PCI interface signals use the 33-MHz PCI AC timing parameters. Timing Assertion/Negation—Constant MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-5...
Page 588 Asserted—Some PCI agents (other than this PCI controller) have decoded its address as Meaning the target of the current access. Negated—No PCI agent has been selected. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-6 Freescale Semiconductor...
Page 589 Negated—The PCI controller is not being selected as a target of configuration read or write transactions. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-7...
Page 590 Negated—Even parity driven by another PCI master or the PCI target during address and data phases. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-8 Freescale Semiconductor...
Page 591 Asserted—An agent n is requesting control of the PCI bus to perform a transaction. State Meaning Negated—An agent n does not require use of the PCI bus. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-9...
Page 592 Asserted—A target is requesting that this PCI controller, as the initiator, stop the current Meaning transaction. Negated—The current transaction can continue. Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-10 Freescale Semiconductor...
Page 593 Configuration Space Registers.” Table 13-4. PCI Configuration Access Registers Offset Register Access Reset Section/Page PCI Configuration Access Registers PCI_CONFIG_ADDRESS 0x0000_0000 13.3.1.1/13-13 PCI_CONFIG_DATA 0x0000_0000 13.3.1.2/13-14 PCI_INT_ACK 0x0000_0000 13.3.1.3/13-15 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-11...
Page 594 This section describes the registers used to allow a local bus master to access the PCI configuration space, and generate special cycle or interrupt acknowledge transactions on the PCI bus. A special case provides MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-12 Freescale Semiconductor...
Page 595 Bus number. Specifies the bus segment to which a configuration transaction is directed. If this field is 0, a Type 0 configuration transaction is generated. Otherwise, a Type 1 configuration transaction is generated. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-13...
Page 596 PCI_CONFIG_ADDRESS[EN] is set. There are some exceptions contained in the description of PCI_CONFIG_ADDRESS[EN]. This register may be accessed with an 8-, 16-, or 32-bit access, depending on the width of the register targeted by the configuration transaction. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-14 Freescale Semiconductor...
Page 597 PCI_ESR fields. Offset 0x00 Access: w1c R MERR APAR PCISERR MPERR TPERR NORSP TABT — — Reset All zeros Figure 13-5. PCI Error Status Register (PCI_ESR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-15...
Page 598 PCI_ECDR fields. Offset 0x04 Access: Read/Write — APAR PCISERR MPERR TPERR NORSP TABT — Reset All zeros Figure 13-6. PCI Error Capture Disable Register (PCI_ECDR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-16 Freescale Semiconductor...
Page 599 Target parity error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1. NORSP No response. Generate an interrupt when the corresponding bit of the PCI_ESR is 1. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-17...
Page 600 0011 4th beat 0100 5th beat 0101 6th beat 0110 7th beat 0111 8th beat 1000 9th beat or beyond (transaction larger than one cache line) Others Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-18 Freescale Semiconductor...
Page 601 Table 13-12. PCI_EACR Field Description Bits Name Description 0–31 PCI_EA PCI error address. Contains the low portion of the address associated with the first detected error. Read only. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-19...
Page 602 PCI_GCR contains fields for controlling the behavior of the internal arbiter, the state of the bus signals, and the PCI reset signal for host mode. Figure 13-12 shows the PCI_GCR fields. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-20 Freescale Semiconductor...
Page 603 PCI_ECR fields. Offset 0x24 Access: Read/Write — APAR PCISERR MPERR TPERR NORSP TABT — Reset All zeros Figure 13-13. PCI Error Control Register (PCI_ECR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-21...
Page 604 Chapter 11, “Sequencer”). Inbound and outbound windows for the same bus should not overlap. Therefore, situations where an inbound window translation points back into an MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-22 Freescale Semiconductor...
Page 605 43–12 of a 64-bit address. In PIBAR0, the upper 12 bits are reserved because only a 32-bit address is supported. The specified address must be aligned to the window size, as defined by PIWAR n [IWS]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-23...
Page 606 1 Address translation is enabled for this window. PCI addresses that match the definition of the window will be recognized by the PCI controller and translated to the local memory space. — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-24 Freescale Semiconductor...
Page 607 PCI configuration registers that are mapped in PCI configuration space. Some fields are common to registers in both spaces to ensure consistency. These fields are discussed in the register definitions. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-25...
Page 608 Maximum latency configuration register PCI function configuration register PCI arbiter control register (PCIACR) Hot swap register block PCI power management register 0 PCI power management register 1 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-26 Freescale Semiconductor...
Page 609 Table 13-23. Vendor ID Configuration Register Field Descriptions Bits Name Description 15–0 Vendor ID. The read-only value 0x1957 specifies Freescale Semiconductor as the manufacturer of the device. 13.3.3.2 Device ID Configuration Register Figure 13-20 shows the device ID fields. This is a read only register.
Page 610 0 The PCI controller does not respond to Memory Space accesses. 1 The PCI controller as a target responds to Memory Space accesses. I/O space. Hard-wired to 0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-28 Freescale Semiconductor...
Page 611 Interrupt status. Contains the status of the device interrupt. The value of this bit is not affected by the INTD bit of the PCI command configuration register. 2–0 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-29...
Page 612 Table 13-28. Standard Programming Interface Configuration Register Field Descriptions Bits Name Description 7–0 Programming interface. This field is hard-wired to 0x00. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-30 Freescale Semiconductor...
Page 613 Table 13-30. Class Code Configuration Register Field Descriptions Bits Name Description 7–0 Base class code. This field is hard-wired to 0x0B, indicating a processor. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-31...
Page 614 Refer to the PCI 2.3 specification for the rules by which the PCI controller completes transactions when the timer has expired. 2–0 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-32 Freescale Semiconductor...
Page 615 Base address. Defines the base address for the internal (on-chip) memory-mapped register space. The size of this space is 1 MB. 19–4 — Reserved Prefetchable. Hard-wired to 0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-33...
Page 616 IWS field. For read operations, these masked bits always return zeros. Figure 13-33 shows the GPL base address register 1–2 fields. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-34 Freescale Semiconductor...
Page 617 Table 13-36. GPL Extended Base Address Registers 1–2 Field Descriptions Bits Name Description 31–0 Extended base address. Defines the high portion of the base address for the inbound window. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-35...
Page 618 The capabilities pointer register specifies the byte offset in the PCI configuration space that contains the first item in the capabilities list. Figure 13-37 shows the capabilities pointer configuration register fields. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-36 Freescale Semiconductor...
Page 619 Offset 0x3D Interrupt Pin Reset Figure 13-39. Interrupt Pin Register 13.3.3.22 Minimum Grant Configuration Register Figure 13-40 shows the minimum grant configuration register fields. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-37...
Page 620 1 Any inbound PCI access to the PCI configuration space is retried. SeeSection 4.3.1.1, “Reset Configuration Word Source,” for more information on reset configuration. 3–4 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-38 Freescale Semiconductor...
Page 621 0 An initiator that requests the bus and receives the grant must begin using the bus within 16 PCI clock periods after the bus becomes idle or its request is subsequently ignored. 1 No requests are ignored. 11–7 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-39...
Page 622 Next pointer—hardwired to 0x80 to point to the address of the power management capability in the PCI controller. 7–0 CAP_ID Capability ID for hot swap (hardwired to 0x06) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-40 Freescale Semiconductor...
Page 623 1 The PCI controller supports the D1 power management state. 24–22 Aux_Current Reports the 3.3 Vaux auxiliary current requirements Device specific initialization. Indicates whether special initialization of this PCI controller is required. — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-41...
Page 624 1 Enable the bus power/clock control policies defined in section 4.7.1 of the PCI Bus Power Management Interface Specification Revision 1.2 Note: This bit field is not implemented, only required for all PCI-to-PCI Bridge MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-42 Freescale Semiconductor...
Page 625 Arbitration for the bus occurs during the previous access so that no PCI bus cycles are consumed waiting for arbitration (except when the bus is idle). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-43...
Page 626 An arbitration example with three masters in the high priority group and two in the low priority group is shown in Figure 13-47. Noting that one position in the high priority group is actually a place-holder for MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-44 Freescale Semiconductor...
Page 627 PCI controller completes one more data phase and relinquishes the bus. The master latency timer can be disabled if needed (see Section 13.3.3.24, “PCI Function Configuration Register,” for more information). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-45...
Page 628 Indicates that the initiator will transfer an entire cache line of data, and if 0b1111 invalidate PCI has any cacheable memory, this line needs to be invalidated. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-46 Freescale Semiconductor...
Page 629 IDSEL is asserted, and AD[1:0] are 0b00; otherwise, the agent ignores the current transaction. The PCI controller determines MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-47...
Page 630 (An idle cycle in PCI is when both PCI_FRAME and PCI_IRDY are negated). Byte lanes not involved in the current data transfer are driven to a stable condition even though the data is not valid. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-48 Freescale Semiconductor...
Page 631 PCI_CLK PCI_AD[31:0] ADDR DATA PCI_C/BE[3:0] BYTE ENABLES PCI_FRAME PCI_IRDY PCI_DEVSEL PCI_TRDY Figure 13-48. Single Beat Read Example MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-49...
Page 632 Figure 13-50 shows an example of a single-beat write transaction. PCI_CLK PCI_AD[31:0] ADDR DATA PCI_C/BE[3:0] BYTE ENABLES PCI_FRAME PCI_IRDY PCI_DEVSEL PCI_TRDY Figure 13-50. Single Beat Write Example MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-50 Freescale Semiconductor...
Page 633 However, if PCI_TRDY is negated when PCI_STOP is asserted, no more data is transferred, and the initiator therefore does not have to wait for a final data transfer (see the retry diagram in Figure 13-50). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-51...
Page 634 This can occur because no buffer entries are available in the I/O sequencer, or the sixteen clock latency timer has expired without MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-52 Freescale Semiconductor...
Page 635 PCI_DEVSEL in the previous cycle, it delays the assertion of PCI_DEVSEL and PCI_TRDY for one cycle to allow the other target to get off the bus. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-53...
Page 636 If the enable bit is set and the device number is not equal to all ones, a configuration cycle translation is performed. When the device number field is equal to all ones, it has a special meaning (see Section 13.4.4.6, “Special Cycle Command,” for more information). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-54 Freescale Semiconductor...
Page 637 A special cycle command is like any other bus command in that it has an address phase and a data phase. The address phase starts like all other commands with the assertion of PCI_FRAME and completes when MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-55...
Page 638 The interrupt vector must be returned when PCI_TRDY is asserted. An interrupt acknowledge transaction can also be issued on the PCI bus by reading from the PCI_INT_ACK register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-56 Freescale Semiconductor...
Page 639 When acting as an initiator during a read transaction or as a target involved in a write to system memory the PCI controller asserts PCI_PERR. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-57...
Page 640 If the PCI controller detects a parity error on a read from PCI, the PCI controller aborts the transaction internally and continues the transfer on the PCI bus, allowing the target to abort/disconnect if desired. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-58 Freescale Semiconductor...
Page 641 The translation windows are disabled after reset, that is, after reset, the PCI controller does not acknowledge externally mastered transactions on the PCI bus by asserting PCI_DEVSEL until the inbound translation windows are enabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 13-59...
Page 642 1. Optionally initialize subsystem vendor ID/device ID a) Initialize PCI inbound window size in PIWAR[1:3] desired window size b) Unlock configuration lock in PCI function configuration register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 13-60 Freescale Semiconductor...
Page 643 — MD5 with 128-bit message digest — HMAC with either algorithm • One channel, supporting a queue of commands (descriptor pointers) — Dynamic assignment of execution units through an integrated controller MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-1...
Page 644 Core DUART DDR-1/DDR-2 eLBC IPIC Security GPIO 16K-I 16K-D Controller Timers System Bus I/O Sequencer (IOS) Figure 14-1. SEC Connected to MPC8313E System Bus MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-2 Freescale Semiconductor...
Page 645 Some descriptor types perform multiple functions to facilitate particular protocols. A descriptor is diagrammed in Table 14-1. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-3...
Page 646 ECB mode, the contents of the IV field do not affect the result of the DES computation. Therefore, when processing descriptors, the channel skips any pointer that has an associated length of zero. For more information, refer to Section 14.3, “Descriptor Overview.” MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-4 Freescale Semiconductor...
Page 647 • The MD5 generates a 128-bit hash, and the algorithm is specified in RFC 1321. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-5...
Page 648 It can signal done through an interrupt or by a writeback of the descriptor header after processing a descriptor. Two values cam be written back: the first is identical to that of the header, with the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-6 Freescale Semiconductor...
Page 649 The channel operates the EU, and makes further requests to the controller to write output data to system memory. When the descriptor processing is complete, the channel asks the controller to release the EU. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-7...
Page 650 Access Register Access Section/Page (AD 17–0) Controller 0x3_1008 IMR—Interrupt mask register 14.6.4.2/14-68 0x3_1010 ISR—Interrupt status register 14.6.4.3/14-70 0x3_1018 ICR—Interrupt clear register 14.6.4.4/14-71 0x3_1020 ID—Identification register 14.6.4.5/14-73 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-8 Freescale Semiconductor...
Page 651 AESURCR—AESU reset control register Word 14.4.3.4/14-43 0x3_4028 AESUSR—AESU status register Word 14.4.3.5/14-44 0x3_4030 AESUISR—AESU interrupt status register Word 14.4.3.6/14-45 0x3_4038 AESUICR—AESU interrupt control register Word 14.4.3.7/14-47 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-9...
Page 652 64 bytes, that is, eight long-words, consisting of one ‘header dword’ and seven ‘pointer dwords.’ See Figure 14-3 for the descriptor format. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-10 Freescale Semiconductor...
Page 653 In processing a descriptor, the SEC can also write back certain fields to the header dword. These are shown in the ‘Writeback’ rows of Figure 14-4, and described in Table 14-5. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-11...
Page 654 14-5), or both, depending upon the states of the CDIE (Channel Done Interrupt Enable) and CDWE (Channel Done Writeback Enable) bits in the channel configuration register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-12 Freescale Semiconductor...
Page 655 Table 14-6. EU_SEL0 and EU_SEL1 Values Value Selected EU (Binary) 0000 No EU selected 0010 0011 MDEU 0110 AESU Others Reserved 1111 Reserved for header writeback MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-13...
Page 656 SRTP encryption and hashing 0011_1 — Reserved 0100_1 — Reserved 0101_1 — Reserved 0110_1 — Reserved 0111_1 — Reserved 1000_1 tls_ssl_block TLS/SSL generic block cipher 1001_1 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-14 Freescale Semiconductor...
Page 657 Extent. A number of bytes in the range 0–127. The use of this field depends on the ‘Descriptor Type’ and ‘Direction’ in the header dword. 24–31 — Reserved 32–63 POINTER Pointer: A memory address. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-15...
Page 658 R (return) bit set. The R bit signifies the end of link table operations so that the channel returns to the descriptor for its next pointer (if any). A single link table entry is shown in Figure 14-6. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-16 Freescale Semiconductor...
Page 659 The last byte of the required parcel size (Extent3) must coincide with the last byte of a memory segment, or unpredictable results may occur. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-17...
Page 660 In FIFO Out FIFO Cipher IV Out Length outbound Auth & CIpher Cipher Only undefined undefined undefined In FIFO MAC Out undefined tls_ssl_ Extent Auth only block MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-18 Freescale Semiconductor...
Page 661 14.4.1.1 DEU Mode Register (DEUMR) The DEU mode register (DEUMR) contains three bits that are used to program DEU operation. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-19...
Page 662 DES (K1 = K3) or 24 bytes (168 bits for 3-key triple DES) will generate an error. Triple DES always uses K1 to encrypt, K2 to decrypt, K3 to encrypt (any write to K1 duplicates that value into K3 in case 2-key 3DES is desired). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-20 Freescale Semiconductor...
Page 663 DEUDSR is cleared when the DEU is reset or re-initialized. Field — Data Size (bits) Reset Addr DEU 0x3_2010 Figure 14-9. DEU Data Size Register (DEUDSR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-21...
Page 664 The RESET_DONE bit in the DEU status register (DEUSR) will indicate when this initialization routine is complete 0 Do not reset 1 Full DEU reset MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-22 Freescale Semiconductor...
Page 665 Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating the EU is ready for operation. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-23...
Page 666 Key size error. An inappropriate value (8 being appropriate for single DES, and 16 and 24 being appropriate for triple DES) was written to the DEU key size register 0 No error detected 1 Key size error MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-24 Freescale Semiconductor...
Page 667 If the corresponding bit is not set, then upon detection of an error, the DEUISR is updated to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt processing. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-25...
Page 668 Output FIFO error. The shared symmetric output FIFO was detected non-empty upon write of DEU data size register 0 Output FIFO non-empty error enabled 1 Output FIFO non-empty error disabled MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-26 Freescale Semiconductor...
Page 669 DEU. Reading this memory location while the module is processing data generates an error interrupt. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-27...
Page 670 The MDEUMR is cleared when the MDEU is reset or re-initialized. Setting a reserved mode bit will generate a data error. If the mode register is modified during processing, a context error is generated. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-28 Freescale Semiconductor...
Page 671 0 Normal operation 1 Perform an HMAC operation. This requires a key and key length. If this is set then the SMAC bit should be 0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-29...
Page 672 1 After the message digest (ICV) is computed, compare it to the data in the MDEU’s input FIFO. If the ICVs do not match, send an error interrupt to the channel. The number of bytes to be compared is given by the ICV size register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-30 Freescale Semiconductor...
Page 673 0 (on) To generate an HMAC for a message that is spread across a sequence of descriptors, the following mode register bit settings should be used: MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-31...
Page 674 CONT bit of the MDEU mode register (MDEUMR) is high, the data size must be a multiple of the 512-bit block size (that is, bits 55–63 must be written as 0). Violating either of these conditions causes a data size error (DSE in the MDEUISR). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-32 Freescale Semiconductor...
Page 675 Software reset is functionally equivalent to hardware reset (the RESET# pin), but only for the MDEU. All registers and internal state are returned to their defined reset state. 0 No reset 1 Full MDEU reset MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-33...
Page 676 Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller interrupt status register (Section 14.6.4.3, “Interrupt Status Register (ISR)”). 0 MDEU is not signaling error 1 MDEU is signaling error MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-34 Freescale Semiconductor...
Page 677 MDEU. Early read error. The MDEU context was read before the MDEU completed the hashing operation. 0 No error detected 1 Early read error MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-35...
Page 678 Field — — IE ERE CE KSE DSE ME AE — — Reset 0x3000 Addr MDEU 0x3_6038 Figure 14-22. MDEU Interrupt Control Register (MDEUICR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-36 Freescale Semiconductor...
Page 679 MDEU performs ICV comparison (see Section 14.4.2.1 "MDEU Mode Register (MDEUMR)"). The MDEU ICV size register is cleared when the MDEU is reset or re-initialized. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-37...
Page 680 A, B, C, D, and E fields as individual registers. Reading this memory location while the module is not done will generate an error interrupt. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-38 Freescale Semiconductor...
Page 681 14.4.2.12 MDEU Key Registers The MDEU maintains eight 64-bit registers for writing an HMAC key. The IPAD and OPAD operations are performed automatically on the key data when required. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-39...
Page 682 If the mode register is modified during processing, a context error will be generated. Field — — Reset Addr AESU 0x3_4000 Figure 14-26. AESU Mode Register (AESUMR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-40 Freescale Semiconductor...
Page 683 Note: This bit is ignored if CM is set to ‘11’ (CTR mode). Table 14-26. AES Cipher Modes Mode ECM (56–57) CM (61–62) CCM (without ICV comparison) CCM with ICV comparison MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-41...
Page 684 AESUKSR is cleared when the AESU is reset or re-initialized. If a key size other than 16, 24, or 32 bytes is specified, an illegal key size error will be generated. If the key size register is modified during processing, a context error will be generated. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-42 Freescale Semiconductor...
Page 685 14-29, allows three levels reset of just AESU, as defined by the three self-clearing bits. Field — Reset Addr AESU 0x3_4018 Figure 14-29. AESU Reset Control Register (AESURCR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-43...
Page 686 0–39 — Reserved 40–47 The number of dwords currently in the output FIFO 48–55 The number of dwords currently in the input FIFO 56–57 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-44 Freescale Semiconductor...
Page 687 Field — — ERE CE KSE DSE ME AE OFE IFE IFU IFO OFU — Reset Addr AESU 0x3_4030 Figure 14-31. AESU Interrupt Status Register (AESUISR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-45...
Page 688 1 Input FIFO non-empty error Input FIFO underflow. The AESU input FIFO has been read while empty. 0 No error detected 1 Input FIFO has had underflow error MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-46 Freescale Semiconductor...
Page 689 1 Internal error disabled Early read error. The AESU IV register was read while the AESU was processing. 0 Early read error enabled 1 Early read error disabled MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-47...
Page 690 (always 128) will be processed. Writing to the AESUEMR causes the AESU to process the final block of a message, allowing it to signal DONE. A read of the AESUEMR will always return a zero value. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-48 Freescale Semiconductor...
Page 691 Must be written at start of new CCM decryption. Header size/MAC size is only used if AES-CCM processing is suspended and resumed. Figure 14-34. AESU Context Registers MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-49...
Page 692 CCM context is such a way that the context can be fetched as a contiguous string into the context registers, prior to encryption/MAC generation or decryption/MAC validation. The context register contents for CCM mode is summarized in Figure 14-35 and further described below. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-50 Freescale Semiconductor...
Page 693 MIC written out to memory by the AESU is the full 128 bits. The host must only append the most-significant 64 bits to the frame as the MIC. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-51...
Page 694 Note that for both encrypt and decrypt operations, if the IEEE Std. 802.11 frame is being processed as a whole (not split across multiple descriptors), the ‘Initialize’ and ‘Final MAC’ bits should be set in the AESU mode register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-52 Freescale Semiconductor...
Page 695 Upon notification of completion of the EU reset sequence, initialize mode registers in the assigned • Initialize EUs and write to EU registers such as key size and text-data size. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-53...
Page 696 If the NT field is 1, done notification is only performed on descriptors in which the DN bit is set in the packet header (Table 14-4). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-54 Freescale Semiconductor...
Page 697 Burst size—The SEC accesses long text-data parcels in main memory through bursts of programmable size: 0 Burst size is 64 bytes 1 Burst size is 128 bytes MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-55...
Page 698 DN (Done Notification) bit is set in the header word of the descriptor, then notify the host by asserting an interrupt. Refer to Section 14.5.2, “Channel Interrupts,” for complete description of channel interrupt operation. — Reserved, set to zero MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-56 Freescale Semiconductor...
Page 699 STATE field. Note: CHN_State is documented for information only. The User will not typically care about the channel state machine. 32–37 — Reserved, set to zero MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-57...
Page 700 0 The assigned secondary EU reset done signal is inactive. 1 The assigned secondary EU reset done signal is active indicating its reset sequence has completed and it is ready to accept data. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-58 Freescale Semiconductor...
Page 701 Table 14-33. G_STATE and S_STATE Field Values Value Gather State Machine: GS_IDLE GS_LOAD_POINTER GS_LOAD_POINTER_DONE GS_LOAD_NEXT_POINTER GS_PROCESS_POINTER GS_TRANS_BLOCK GS_TRANS_BLOCK_DONE GS_TRANS_BYTES GS_TRANS_BYTES_DONE GS_INC_PAIR_PTR GS_UPDATE GS_DONE GS_ERROR GS_RELOAD GS_TRANS_INBOUND GS_TRANS_INBOUND_DONE MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-59...
Page 702 0x16 TRANS_REQUEST_WRITE_SNOOPIN 0x39 MAC_TO_CIPHER_DONE 0x17 DELAY_PRI_SEC_DONE 0x3A READ_PRI_STATUS 0x18 TRANS_REQUEST_WRITE 0x3C READ_SEC_STATUS 0x19 WRITE_KEY_SIZE Others Reserved 0x1B DELAY_PRI_DONE 0x1E WRITE_DATASIZE_SEC_SNOOPOUT 0x1F TRANS_REQUEST_READ_SNOOPOUT 0x20 DELAY_SEC_DONE 0x21 TRANS_REQUEST_READ MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-60 Freescale Semiconductor...
Page 703 Table 14-36. Crypto-Channel Pointer Status Register PAIR_PTR Field Values Value Error 0x00 Processing header or pointer dword 0 0x01 Processing pointer dword 1 0x02 Processing pointer dword 2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-61...
Page 704 In typical operation, the host CPU will create a descriptor in memory containing all relevant mode and location information for the SEC, then ‘launch’ the SEC by writing the address of the descriptor to the fetch FIFO. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-62 Freescale Semiconductor...
Page 705 — Pointer2 Length3 Extent3 — Pointer3 Length4 Extent4 — Pointer4 Length5 Extent5 — Pointer5 Length6 Extent6 — Pointer6 Address Channel_1 0x3_1180–0x3_11BF Figure 14-40. Descriptor Buffer (DB) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-63...
Page 706 The controller interfaces to the host through the master/slave bus interface and to the channels and EUs through internal buses. All MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-64 Freescale Semiconductor...
Page 707 1, 2, and 4 channels. Although not necessary for a single-channel SEC, dynamic assignment of EUs to the channel is maintained to improve software compatibility with other SEC-enhanced processors. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-65...
Page 708 All interrupt outputs from other SEC blocks are fed to the controller as interrupt conditions. In addition, the controller itself detects some interrupt conditions. The controller maintains an interrupt status register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-66 Freescale Semiconductor...
Page 709 14-41, is used to check the assignment status of a EU to the channel. A 1-bit field indicates to the channel whether or not the EU is assigned. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-67...
Page 710 For normal operation, the IMR should be programmed as follows: Unmask the channel interrupts while masking EU interrupts. The channels will generate the appropriate interrupts to the host. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-68 Freescale Semiconductor...
Page 711 Field — Subfield Reset 0x0000 Addr 0x 3_100C Field — MDEU — AESU — Subfield Reset 0x0000 Addr 0x 3_100C Figure 14-42. Interrupt Mask Register (IMR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-69...
Page 712 (ICR). Figure 14-43 shows the bit positions of each potential interrupt source. The bit fields are described in Table 14-39. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-70 Freescale Semiconductor...
Page 713 When an ICR bit is written, it will automatically clear itself one cycle later. That is, it is not necessary to write a ‘0’ to a bit position which has been written with a ‘1’. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-71...
Page 714 Field — Subfield Reset 0x0000 Addr 0x 3_101C Field — MDEU — AESU — Subfield Reset 0x0000 Addr 0x 3_101C Figure 14-44. Interrupt Clear Register (ICR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-72 Freescale Semiconductor...
Page 715 SEC 2.2. The value of this register is always 0x0000_0000_0002_00A0, indicating that this is the first version of SEC2.2. Field — VERSION Reset 0x0000_0000_0002_00A0 Addr 0x 3_1BF8 Figure 14-46. IP Block Revision Register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-73...
Page 716 SEC transactions can be snooped by the MPC8313E cache if defined as global. This definition is programmed in the master control register MCR[GI]. See 14.6.4.7, “Master Control Register (MCR),” more details. Note that SEC transactions are defined as global by default. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-74 Freescale Semiconductor...
Page 717 14.7 Power Saving Mode The SEC can be disabled by clearing SCCR[ENCCM]. See Section 4.5.2.3, “System Clock Control Register (SCCR),” for more information. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 14-75...
Page 718 Security Engine (SEC) 2.2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 14-76 Freescale Semiconductor...
Page 719 PowerQUICC II Pro TSEC, allowing existing driver software to be re-used with minimal change. Each eTSEC is organized as shown in Figure 15-1. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-1...
Page 720 • Support for different Ethernet physical interfaces: — 10/100 Mbps IEEE 802.3 MII and RMII — 10/100 Mbps RGMII — 1000 Mbps full-duplex RGMII and RTBI MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-2 Freescale Semiconductor...
Page 721 — Programmable Ethernet preamble insertion and extraction of up to 7 bytes • MAC address recognition: — Exact match on primary and virtual 48-bit unicast addresses – VRRP and HSRP support for seamless router fail-over MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-3...
Page 722 If configured in full-duplex mode (10/100/1000 Mbps operation; MACCFG2[Full Duplex] is set), the MAC supports flow control. If flow control is enabled, it allows the MAC to receive or send PAUSE frames. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-4 Freescale Semiconductor...
Page 723 These options are described further in Section 15.5.3.2.1, “Transmit Control Register (TCTRL).” • RMON support Standard Ethernet interface management information base (MIBs) can be generated through the RMON MIB counters. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-5...
Page 724 RGMII (RX_CLK falling)—Receive data bits 7:4, input RTBI (RX_CLK rising)—RCG bits 3:0, input RTBI (RX_CLK falling)—RCG bits 8:5, input RMII—RXD[1:0] receive data bits, input RMII—RXD[3:2] are unused MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-6 Freescale Semiconductor...
Page 725 Timer current time is equal to or greater than alarm time comparator register. User reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external output pin). SD_REF_CLK, SerDes PLL reference clock (and complement) — SD_REF_CLK MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-7...
Page 726 This signal feeds back the uninverted transmit clock in MII mode, but feeds back an inverted transmit clock in RTBI or RGMII modes. This signal is driven low unless transmission is enabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-8 Freescale Semiconductor...
Page 727 RCG[8:5] are received on the falling edge of TSEC n _RX_CLK. In RMII mode, TSEC n _RXD[1:0] represents RXD[1:0], which is considered valid when TSEC n _RX_DV (CRS_DV) is asserted, or invalid otherwise. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-9...
Page 728 1588 pulse out 2. Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external output pin) TSEC_1588_PP3 1588 pulse out 3. Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external output pin) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-10 Freescale Semiconductor...
Page 729 300–4FF eTSEC receive control/status registers 500–5FF MAC registers 600–7FF RMON MIB registers 800–8FF Hash table registers 900–9FF — A00–AFF FIFO control/status registers B00–BFF DMA system registers MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-11...
Page 730 — — 0x2_4020 ECNTRL—Ethernet control register 0x0000_0000 15.5.3.1.6/15-31 0x2_4024 Reserved — — — 0x2_4028 PTV—Pause time value register 0x0000_0000 15.5.3.1.7/15-33 0x2_402C DMACTRL—DMA control register 0x0000_0000 15.5.3.1.8/15-34 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-12 Freescale Semiconductor...
Page 731 — — — 0x2_41BC TBPTR7*—TxBD pointer for ring 7 0x0000_0000 15.5.3.2.9/15-45 0x2_41C0– Reserved — — — 0x2_4200 0x2_4204 TBASE0—TxBD base address of ring 0 0x0000_0000 15.5.3.2.10/15-46 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-13...
Page 732 0x2_4310 RXIC—Receive interrupt coalescing register 0x0000_0000 15.5.3.3.3/15-52 0x2_4314 RQUEUE*—Receive queue control register. 0x0080_0080 15.5.3.3.4/15-53 0x2_4318– Reserved — — — 0x2_432C 0x2_4330 RBIFX*—Receive bit field extract control register 0x0000_0000 15.5.3.3.5/15-54 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-14 Freescale Semiconductor...
Page 733 — — — 0x2_4424 RBASE4*—RxBD base address of ring 4 0x0000_0000 15.5.3.3.12/15-63 0x2_4428 Reserved — — — 0x2_442C RBASE5*—RxBD base address of ring 5 0x0000_0000 15.5.3.3.12/15-63 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-15...
Page 734 0x2_4538 Reserved — — — 0x2_453C IFSTAT—Interface status 0x0000_0000 15.5.3.5.12/15-76 0x2_4540 MACSTNADDR1—MAC station address register 1 0x0000_0000 15.5.3.5.13/15-77 0x2_4544 MACSTNADDR2—MAC station address register 2 0x0000_0000 15.5.3.5.14/15-78 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-16 Freescale Semiconductor...
Page 735 0x2_4680 TR64—Transmit and receive 64-byte frame counter 0x0000_0000 15.5.3.6.1/15-80 0x2_4684 TR127—Transmit and receive 65- to 127-byte frame counter 0x0000_0000 15.5.3.6.2/15-80 0x2_4688 TR255—Transmit and receive 128- to 255-byte frame counter 0x0000_0000 15.5.3.6.3/15-81 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-17...
Page 736 0x0000_0000 15.5.3.6.31/15-94 0x2_46FC TSCL—Transmit single collision packet counter 0x0000_0000 15.5.3.6.32/15-95 0x2_4700 TMCL—Transmit multiple collision packet counter 0x0000_0000 15.5.3.6.33/15-95 0x2_4704 TLCL—Transmit late collision packet counter 0x0000_0000 15.5.3.6.34/15-96 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-18 Freescale Semiconductor...
Page 737 0x2_4810 IGADDR4—Individual/group address register 4 0x0000_0000 0x2_4814 IGADDR5—Individual/group address register 5 0x0000_0000 0x2_4818 IGADDR6—Individual/group address register 6 0x0000_0000 0x2_481C IGADDR7—Individual/group address register 7 0x0000_0000 0x2_4820– Reserved — — — 0x2_487C MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-19...
Page 738 0x2_4C5C RFBPTR3*—Last Free RxBD pointer for ring 3 0x0000_0000 15.5.3.9.2/15-109 0x2_4C60 Reserved — — — 0x2_4C64 RFBPTR4*—Last Free RxBD pointer for ring 4 0x0000_0000 15.5.3.9.2/15-109 0x2_4C68 Reserved — — — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-20 Freescale Semiconductor...
Page 739 0xFFFF_FFFF 0x2_4E50– Reserved — — — 0x2_4E7C 0x2_4E80 TMR_FIPER1*—Timer fixed period interval 0xFFFF_FFFF 15.5.3.10.13/15-120 0x2_4E84 TMR_FIPER2*—Timer fixed period interval 0xFFFF_FFFF 0x2_4E88 TMR_FIPER*3—Timer fixed period interval 0xFFFF_FFFF MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-21...
Page 740 The controller ID register (TSEC_ID) is a read-only register. The TSEC_ID register is used to identify the eTSEC block and revision. Offset eTSEC1:0x2_4000; eTSEC2:0x2_5000 Access: Read only 15 16 23 24 TSEC_ID TSEC_REV_MJ TSEC_REV_MN Reset 0 Figure 15-2. TSEC_ID Register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-22 Freescale Semiconductor...
Page 741 50 eTSEC multiple ring and filer supports are OFF and Rx TOE and Tx TOE supports are on Table 15-7 describes the field settings for TSEC_ID2[TSEC_INT]. Table 15-7. TSEC_ID2[TSEC_INT] Field Settings Mode 0 Ethernet mode not supported 1 Ethernet mode supported 11–13 Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-23...
Page 742 Some of the error interrupts are independently counted in the MIB block counters. Software may choose to mask off these interrupts because these errors are visible to network management through the MIB counters. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-24 Freescale Semiconductor...
Page 743 • A transmission of a flow control PAUSE frame, which was initiated by setting TCTRL[TFC_PAUSE], is now complete. 0 No graceful stop interrupt. 1 Graceful stop requested. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-25...
Page 744 0 No Magic Packet received, or Magic Packet mode was not enabled. 1 A Magic Packet was received while in Magic Packet mode. MACCFG2[MPEN] is also cleared upon receiving the Magic Packet. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-26 Freescale Semiconductor...
Page 745 The interrupt mask register provides control over which possible interrupt events in the IEVENT register are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-27...
Page 746 MIB counter overflow interrupt enable GTSCEN Graceful transmit stop complete interrupt enable BTEN Babbling transmitter interrupt enable TXCEN Transmit control interrupt enable TXEEN Transmit error interrupt enable MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-28 Freescale Semiconductor...
Page 747 BSYDIS EBERRDIS — BABTDIS — TXEDIS — LCDIS CRLDIS XFUNDIS Reset All zeros — FIRDIS FIQDIS DPEDIS PERRDIS Reset All zeros Figure 15-6. EDIS Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-29...
Page 748 0 Allow eTSEC to report IEVENT[FIQ] status. 1 Do not set IEVENT[FIQ] if eTSEC attempts to file a received frame to an invalid (disabled) RxBD ring, but discard the frame silently. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-30 Freescale Semiconductor...
Page 749 1 The addressed counter value is automatically cleared to zero after a host read. This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be changed without proper care. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-31...
Page 750 Table 15-12. eTSEC Interface Configurations ECNTRL Field MACCFG2 Field Interface Mode FIFM GMIIM TBIM R100M SGMIIM I/F Mode RTBI 1Gbps — — RGMII 1Gbps — — MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-32 Freescale Semiconductor...
Page 751 Pause time value. Represents the 16-bit pause quanta (that is, 512 bit times). This pause value is used as part of the PAUSE frame to be sent when TCTRL[TFC_PAUSE] is set. See Section 15.6.2.9, “Flow Control,” on page 15-154 for more information. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-33...
Page 752 0 eTSEC scans input data stream for valid frame. 1 eTSEC stops receiving frames following completion of current frame. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-34 Freescale Semiconductor...
Page 753 TCTRL register. Offset eTSEC1:0x2_4100; eTSEC2:0x2_5100 Access: Mixed RFC_PAUSE — IPCSEN TUCSEN VLINS THDF — TFC_PAUSE TXSCHED — Reset All zeros Figure 15-10. TCTRL Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-35...
Page 754 DMACTRL[GTS] or reception of a PAUSE frame. 0 No request for Tx PAUSE frame pending or transmission complete. 1 Software request for Tx PAUSE frame pending. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-36 Freescale Semiconductor...
Page 755 THLT3 THLT4 THLT5 THLT6 THLT7 — Reset All zeros TXF0 TXF1 TXF2 TXF3 TXF4 TXF5 TXF6 TXF7 — Reset All zeros Figure 15-11. TSTAT Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-37...
Page 756 Repeatable error conditions which cause halt include: Bus error: • Invalid BD or data address • Uncorrectable error on BD or data read TxBD programming errors: • Ready=1 and length=0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-38 Freescale Semiconductor...
Page 757 Repeatable error conditions which cause halt include: Bus error: • Invalid BD or data address • Uncorrectable error on BD or data read TxBD programming errors: • Ready=1 and length=0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-39...
Page 758 TXF6 Transmit frame event occurred on ring 6. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting a frame from this ring. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-40 Freescale Semiconductor...
Page 759 This is the default value used for the virtual-LAN identifier in VLAN-tagged frames. A value of zero is defined as the null VLAN, however field PRI may be still set independently. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-41...
Page 760 TxBD[I] bit set. The threshold value is represented in units of 64 clock periods as specified by the timer clock source (TXIC[ICCS[). The value of ICTT must be greater than zero to avoid unpredictable behavior. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-42 Freescale Semiconductor...
Page 761 When modified weighted round-robin Tx scheduling is enabled (TCTRL[TXSCHED] = 10), this register determines the weighting applied to each transmit queue for queues 0 to 3. For priority-based scheduling, MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-43...
Page 762 Queuing (MWRR).” Figure 15-16 describes the definition for the TR47WT register. Offset eTSEC1:0x2_4144; eTSEC2:0x2_5144 Access: Read/Write 15 16 23 24 Reset All zeros Figure 15-16. TR47WT Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-44 Freescale Semiconductor...
Page 763 TBPTR0–TBPTR7 while eTSEC is actively transmitting frames. However, TBPTR0– TBPTR7 can be modified when the transmitter is disabled or when no Tx buffer is in use (after a GRACEFUL STOP MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-45...
Page 764 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how many BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the eTSEC transmit function on the associated ring. 29–31 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-46 Freescale Semiconductor...
Page 765 TMR_TXTSn_H/L register. Table 15-26. TMR_TXTS n _H/L Register Field Descriptions Bits Name Description 0–63 TXTS_H/L Timestamp field of the transmitted PTP packet’s start of frame detection. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-47...
Page 766 Note that the minimum zero padding value for this field should be PAL–8 if the TS field is set and 0 when PAL is < 8. — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-48 Freescale Semiconductor...
Page 767 Note that if PRSDEP is cleared, VLEX must be cleared as well. (VLAN tag extraction is only supported when the parser is enabled.) Also, if PRSDEP is cleared, FILREN must also be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-49...
Page 768 QHLT0 QHLT1 QHLT2 QHLT3 QHLT4 QHLT5 QHLT6 QHLT7 — Reset All zeros RXF0 RXF1 RXF2 RXF3 RXF4 RXF5 RXF6 RXF7 — Reset All zeros Figure 15-23. RSTAT Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-50 Freescale Semiconductor...
Page 769 Reserved RXF0 Receive frame event occurred on ring 0. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a frame to this ring. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-51...
Page 770 0 The coalescing timer advances count every 64 eTSEC Rx interface clocks (TSECn_GTX_CLK). 1 The coalescing timer advances count every 64 system clocks. This mode is recommended for FIFO operation. — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-52 Freescale Semiconductor...
Page 771 Receive queue 4 enable. 0 RxBD ring is not queried for reception. In effect the receive queue is disabled. 1 RxBD ring is queried for reception. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-53...
Page 772 B0OFFSET Offset relative to the header defined by B0CTL that locates byte 0 of property ARB. An effective offset of zero points to the first byte of the specified header. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-54 Freescale Semiconductor...
Page 773 RQPROP. To access the RQCTRL and RQPROP words of entry n, write n to RQFAR. Then read or write the indexed RQCTRL and RQPROP words by reading or writing the RQFCR and RQFPR registers, respectively. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-55...
Page 774 RxBD ring, and software needs to consult the RQ field of the Rx frame control block to determine which virtual receive queue was chosen. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-56 Freescale Semiconductor...
Page 775 RQFPR register according to property ID. Offset eTSEC1:0x2_433C; eTSEC2:0x2_533C; Access: Read/Write RQPROP Reset (undefined) Figure 15-29. Receive Queue Filer Table Property IDs 0, 2–15 Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-57...
Page 776 UDP Set if a UDP header was parsed. 28–29 — Reserved. PER Set on a parse error, such as header inconsistency. EER Set on an Ethernet framing error that prevents parsing. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-58 Freescale Semiconductor...
Page 777 SAH Source MAC address, most significant 24 bits. Defaults to 0x000000. 0110 0–7 — Reserved, should be written with zero. 8–31 Source MAC address, least significant 24 bits. Defaults to 0x000000. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-59...
Page 778 Note that for IPv6 the Traffic Class field is extracted using the IP header definition in RFC 2460. IPv6 headers formed using the earlier RFC 1883 have a different format and must be handled with software. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-60 Freescale Semiconductor...
Page 779 Section 15.5.3.5.5, “Maximum Frame Length Register (MAXFRM),” for further discussion. 26–31 — To ensure that MRBL is a multiple of 64, these bits are reserved and should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-61...
Page 780 RxBD eTSEC receives. Offset eTSEC1:0x2_4384+8× n ; eTSEC2:0x2_5384+8× n Access: Read/Write 28 29 RBPTR n — Reset All zeros Figure 15-33. RBPTR0–RBPTR7 Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-62 Freescale Semiconductor...
Page 781 Ethernet frame. This register is only updated when the precision timestamp logic is enable via TMR_CTRL[TE]. This register is read only in normal operation. Figure 15-35 describes the definition for the RXTS_H/L register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-63...
Page 782 CRS deferral process. This optional IPG mechanism enhances system robustness and ensures fair access to the medium. During the first two-thirds of the IPG, the IPG timer is cleared if CRS MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-64 Freescale Semiconductor...
Page 783 In the event the preamble transmission happens to cause a collision, the eTSEC ensures the minimum 96-bit presence on the wire, then drops preamble and waits a back-off time depending on the value of the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-65...
Page 784 While enabled, the length of MII management frames are reduced from 64 clocks to 32 clocks. This effectively doubles the efficiency of the interface. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-66 Freescale Semiconductor...
Page 785 Reserved Loop Back Loop back. This bit is cleared by default. 0 Normal operation. 1 Loop back the MAC transmit outputs to the MAC receive inputs. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-67...
Page 786 Length Full — PreAmRxEN PreAmTxEN MPEN PAD/CRC CRC EN Length Mode Frame check Duplex Reset 0 1 1 1 0 0 Figure 15-37. MACCFG2 Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-68 Freescale Semiconductor...
Page 787 0 No length field checking is performed. 1 The MAC checks the frame’s length field on receive to ensure it matches the actual data field length. Transmitted frames are not checked. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-69...
Page 788 IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x00 to IPGR2. Its default is 0x40 (64d) which follows the two-thirds/one-third guideline. — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-70 Freescale Semiconductor...
Page 789 Back pressure no backoff. This bit is cleared by default. BackOff 0 The Tx MAC follows the binary exponential back off rule. 1 The Tx MAC immediately re-transmits, following a collision, during back pressure operation. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-71...
Page 790 PHYs be accessed and configured. Note: when an eTSEC is configured to use RTBI, configuration of the RTBI (described in Section 15.5.4, “Ten-Bit Interface (TBI)”) is done through the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-72 Freescale Semiconductor...
Page 791 The MIIMCOM register is written by the user. Figure 15-42 describes the definition for MIIMCOM. Offset eTSEC1:0x2_4524 Access: Read/Write — Scan Cycle Read Cycle Reset All zeros Figure 15-42. MIIMCOM Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-73...
Page 792 27–31 Register Address This field represents the 5-bit register address field of Mgmt cycles. Up to 32 registers can be accessed. Its default value is 0x00. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-74 Freescale Semiconductor...
Page 793 0–15 — Reserved 16–31 PHY Status Following an MII Mgmt read cycle, the 16-bit data can be read from this location. Its default value is 0x0000. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-75...
Page 794 Figure 15-47. Interface Status Register Definition Table 15-51 describes the fields of the FSTAT register. Table 15-51. IFSTAT Field Descriptions Bits Name Description 0–21 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-76 Freescale Semiconductor...
Page 795 Station Address, 3rd Octet This field holds the third octet of the station address. The third – octet (station address bits 16 23) defaults to a value of 0x0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-77...
Page 796 Exact Match Address, Exact Match Address, 6th Octet 5th Octet 4th Octet 3rd Octet Reset All zeros Figure 15-50. MAC Exact Match Address n Part 1 Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-78 Freescale Semiconductor...
Page 797 RMON MIB group 1, RMON MIB group 2 if table counters, RMON MIB group 3, RMON MIB group 9, RMON MIB 2, and the IEEE 802.3 Ethernet MIB. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-79...
Page 798 TR127 register. Offset eTSEC1:0x2_4684; eTSEC2:0x2_5684 Access: Read/Write — TR127 Reset All zeros Figure 15-53. Transmit and Receive 65- to 127-Byte Frame Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-80 Freescale Semiconductor...
Page 799 10–31 TR511 Increments for each good or bad frame transmitted and received which is 256–511 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-81...
Page 800 TRMAX Increments for each good or bad frame transmitted and received which is 1024–1518 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-82 Freescale Semiconductor...
Page 801 Figure 15-60 describes the definition for the RPKT register. Offset eTSEC1:0x2_46A0; eTSEC2:0x2_56A0 Access: Read/Write — RPKT Reset All zeros Figure 15-60. Receive Packet Counter Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-83...
Page 802 Receive multicast packet counter. Increments for each multicast frame with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN), excluding broadcast frames. This count does not include range/length errors. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-84 Freescale Semiconductor...
Page 803 Receive control frame packet counter. Increments for each MAC control frame received (PAUSE and unsupported) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-85...
Page 804 Receive unknown opcode counter. Increments each time a MAC control frame is received which contains an opcode other than PAUSE, but the frame has valid CRC and length 64 to 1518 (non VLAN) or 1522 (VLAN). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-86 Freescale Semiconductor...
Page 805 (46–1500 bytes). The counter does not increment if the length field is not a valid 802.3 length, such as an Ethertype value. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-87...
Page 806 1 on TSEC n _RX_ER and an 0xE on TSEC n _RXD. Only one false carrier condition can be detected and logged between frames. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-88 Freescale Semiconductor...
Page 807 Receive oversize packet counter. Increments each time a frame is received which exceeded 1518 (non VLAN) or 1522 (VLAN) and contains a valid FCS and was otherwise well formed. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-89...
Page 808 RJBR Receive jabber counter. Increments for frames received which exceed 1518 (non VLAN) or 1522 (VLAN) bytes and contain an invalid FCS. This includes alignment errors. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-90 Freescale Semiconductor...
Page 809 65,535 bytes of frame and phantom preamble. Note that the value of TBYT may be greater than the actual number of bytes transmitted if the frame is truncated because it exceeds MAXFRM. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-91...
Page 810 Transmit multicast packet counter. Increments for each multicast valid frame transmitted (excluding broadcast frames) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-92 Freescale Semiconductor...
Page 811 Transmit PAUSE frame packet counter. Increments each time a valid PAUSE MAC control frame is transmitted with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-93...
Page 812 0–19 — Reserved 20–31 TEDF Transmit excessive deferral packet counter. Increments for frames aborted which were deferred for an excessive period of time (3036 byte times). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-94 Freescale Semiconductor...
Page 813 Transmit multiple collision packet counter. Increments for each frame transmitted which experienced 2–15 collisions (including any late collisions) during transmission as defined using the Half_Duplex[RETRANSMISSION MAXIMUM] field. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-95...
Page 814 Bits Name Description 0–19 — Reserved 20–31 TXCL Transmit excessive collision packet counter. Increments for each frame that experienced 16 collisions during transmission and was aborted. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-96 Freescale Semiconductor...
Page 815 Table 15-92. TDRP Field Descriptions Bits Name Description 0–15 — Reserved 16–31 TDRP Transmit drop frame counter. Increments each time a memory error or an underrun has occurred. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-97...
Page 816 Table 15-94. TFCS Field Descriptions Bits Name Description 0–19 — Reserved 20–31 TFCS Transmit FCS error counter. Increments for every valid sized packet with an incorrect FCS value. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-98 Freescale Semiconductor...
Page 817 Table 15-96. TOVR Field Descriptions Bits Name Description 0–19 — Reserved 20–31 TOVR Transmit oversize frame counter. Increments for each oversized transmitted frame with a correct FCS value. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-99...
Page 818 Table 15-98. TFRG Field Descriptions Bits Name Description 0–19 — Reserved 20–31 TFRG Transmit fragment counter. Increments for every frame less then 64 bytes, with an incorrect FCS value. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-100 Freescale Semiconductor...
Page 819 Carry register 1 RXPF counter carry bit C1RXU Carry register 1 RXUO counter carry bit C1RAL Carry register 1 RALN counter carry bit C1RFL Carry register 1 RFLR counter carry bit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-101...
Page 820 Carry register 2 TUND counter carry bit C2TFG Carry register 2 TFRG counter carry bit C2TBY Carry register 2 TBYT counter carry bit C2TPK Carry register 2 TPKT counter carry bit MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-102 Freescale Semiconductor...
Page 821 Mask register 1 TR127 counter carry bit mask M1255 Mask register 1 TR255 counter carry bit mask M1511 Mask register 1 TR511 counter carry bit mask MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-103...
Page 822 Mask register 1 RFRG counter carry bit mask M1RJB Mask register 1 RJBR counter carry bit mask M1RDR Mask register 1 RDRP counter carry bit mask MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-104 Freescale Semiconductor...
Page 823 Mask register 2 TLCL counter carry bit mask M2TXC Mask register 2 TXCL counter carry bit mask M2TNC Mask register 2 TNCL counter carry bit mask MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-105...
Page 824 IGADDR0–IGADDR7 hold hash table entries 0–255 for group addresses, while registers GADDR0–GADDR7 hold entries 256–511 of the extended group hash table. Section 15.6.2.7.2, “Hash Table Algorithm,” for more information on the hash algorithm. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-106 Freescale Semiconductor...
Page 825 GADDRn register. Offset eTSEC1:0x2_4880+ 4 × n ; eTSEC2:0x2_5880+ 4 × n Access: Read/Write GADDR n Reset All zeros Figure 15-101. GADDR n Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-107...
Page 826 1 Enables snooping of all receive frames data to memory. RBDSEN RxBD snoop enable. 0 Disables snooping of all receive BD memory accesses. 1 Enables snooping of all receive BD memory accesses. 26–31 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-108 Freescale Semiconductor...
Page 827 The eTSEC then performs modulo arithmetic involving RBASEn, RBPTRn and RFBPTRn to determine the number of free BDs remaining in the ring. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-109...
Page 828 Figure 15-7 describes the definition for the TMR_CTRL register. Register fields not described below are reserved. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-110 Freescale Semiconductor...
Page 829 TxBD. For guidelines on using the RTPE bit, refer to Section 15.6.6.5, “Timestamp Insertion on Transmit Packets.” FIPER Realignment Disable 0 Fiper Realignment is enabled. 1 Fiper Realignment is disabled. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-111...
Page 830 The eTSEC precision timer implementation can generate additional interrupts that are independent of the frame based events that controlled via IEVENT. The timer interrupts are not affected by any interrupt MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-112 Freescale Semiconductor...
Page 831 0 periodic pulse not generated 1 periodic pulse generated Indicates that a periodic pulse has been generated based on FIPER2 register. 0 periodic pulse not generated 1 periodic pulse generated MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-113...
Page 832 Timer ALM1 event enable ALM1EN Timer ALM2 event enable 16–23 — Reserved PP1EN Periodic pulse event 1 enable PP2EN Periodic pulse event 2 enable 26–31 — Reserved MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-114 Freescale Semiconductor...
Page 833 TMR_PEVENT register are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this register are R/W and cleared upon a hardware reset. Figure 15-108 describes the definition for the TMR_PEMASK register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-115...
Page 834 Writing 1 to any bit of this register clears it. Figure 15-115 describes the definition for the TMR_STAT register. Offset eTSEC1:0x2_4E14 Access: Mixed 25 26 — STAT_VEC Reset All zeros Table 15-115. TMR_STAT Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-116 Freescale Semiconductor...
Page 835 1.0001. The ADDEND value is added to the 32-bit accumulator register at every rising edge of the oscillator clock (TimerOsc). The clock counter is incremented at every carry pulse of the accumulator. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-117...
Page 836 Timer generated output clock prescale register. It is used to adjust output clock frequency that is put onto the 1588 clock output signal. The register in eTSEC1 is shared for all eTSECs. Figure 15-112 describes the definition for the TMR_PRSC register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-118 Freescale Semiconductor...
Page 837 There are two of these registers for eTSEC1 which are shared amongst all eTSECs. Figure 15-114 describes the definition for the TMR_ALARMn_H/L register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-119...
Page 838 FIPER by writing a new value to the register. The ratio between the prescale register value and the FIPER value should be devisable by the clk period. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-120 Freescale Semiconductor...
Page 839 TMR_ETTSn_H/L register. Table 15-124. TMR_ETTS1-2_H Register Field Descriptions Bits Name Description 0–63 ETTS_H/L Time stamp field at the programmable edge of the external trigger. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-121...
Page 840 Receive GMII interface. In GMII mode, the GMII signals are passed through to the MAC. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-122 Freescale Semiconductor...
Page 841 AN link partner base page ability 16 bits 15.5.4.3.4/15-128 (ANLPBPA) 0x06 AN expansion (ANEX) R, LH 16 bits 15.5.4.3.5/15-129 0x07 AN next page transmit (ANNPT) R/W, R 16 bits 15.5.4.3.6/15-130 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-123...
Page 842 1 The auto-negotiation process restarts. This action is only available if auto-negotiation is enabled. Full Duplex mode. This bit is set by default. Duplex 0 Reserved. 1 Full-duplex operation. — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-124 Freescale Semiconductor...
Page 843 Remote fault. This bit is read-only and is cleared by default. Each read of the status register clears this bit. Fault 0 Normal operation. 1 A remote fault condition was detected. This bit latches high in order for software to detect the condition. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-125...
Page 844 The default value is 00. Indicate a fault by setting a non-zero remote fault encoding and re-negotiating. RF1 bit[3] RF2 bit[2] Description No error, link OK Offline Link_Failure Auto-Negotiation_Error MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-126 Freescale Semiconductor...
Page 845 Disable PAUSE receive Enable PAUSE transmit Enable PAUSE transmit Enable PAUSE receive Enable PAUSE receive Disable PAUSE transmit Disable PAUSE transmit Disable PAUSE receive Disable PAUSE receive MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-127...
Page 846 This bit is read-only. RF1 bit[3] RF2 bit[2] Description No error, link OK Offline Link_Failure Auto-Negotiation_Error 4–6 — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-128 Freescale Semiconductor...
Page 847 1 A new page was received and stored in the applicable AN link partner ability or AN next page register. This bit latches high in order for software to detect while polling. — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-129...
Page 848 Access: Read only R Next Page Msg Page Ack2 Toggle Message/Un-formatted Code Field — Reset All zeros Figure 15-123. AN Link Partner Ability Next Page Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-130 Freescale Semiconductor...
Page 849 EXST register. Offset 0x0F Access: Read only R 1000X Full 1000X Half 1000T Full 1000T Half — Reset Figure 15-124. Extended Status Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-131...
Page 850 JD register. Offset 0x10 Access: Read/Write Jitter Jitter Select — Custom Jitter Pattern Enable Reset All zeros Figure 15-125. Jitter Diagnostics Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-132 Freescale Semiconductor...
Page 851 Offset 0x11 Access: Mixed Disable Disable Clock Mode Soft_Reset — — — — Rx Dis Tx Dis Sense Select Reset Figure 15-126. TBI Control Register Definition MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-133...
Page 852 0 is the lsb). If a mode does not use all input signals available to a particular eTSEC, those inputs that are not used must be pulled low on the board. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-134 Freescale Semiconductor...
Page 853 PHY. The RMII is implemented as defined by the RMII Specification of the RMII Consortium, as of March 20, 1998. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-135...
Page 854 Ethernet controllers’ module connection with a PHY. The RGMII is implemented as defined by the RGMII specification Version 1.2a 9/22/00. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-136 Freescale Semiconductor...
Page 855 RTBI including the signals required to establish eTSEC module connection with a PHY. Note that in RTBI the eTSEC immediately begins auto-negotiation with the SerDes. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-137...
Page 856 Version 1.2a 9/22/00, and is intended to be an alternative to the IEEE 802.3u MII, the IEEE 802.3z GMII and the TBI standard for connecting to an Ethernet PHY. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-138 Freescale Semiconductor...
Page 857 Voltage[V] 3.3 Signals No. of Signals No. of Signals No. of (TSEC n _) (TSEC n _) (TSEC n _) Signals Signals Signals GTX_CLK TX_CLK TX_CLK REF_CLK MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-139...
Page 858 TX_CLK RX_CLK1 TxD[0] TxD[0] TCG[0] TCG[0]/TCG[5] TxD[1] TxD[1] TCG[1] TCG[1]/TCG[6] TxD[2] TxD[2] TCG[2] TCG[2]/TCG[7] TxD[3] TxD[3]/ TCG[3] TCG[3]/TCG[8] TX_EN TX_CTL TCG[8] TCG[4]/TCG[9] (TX_EN/ TX_ERR) TX_ER TCG[9] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-140 Freescale Semiconductor...
Page 859 TxD[0 TCG[0]/TCG[5] TxD[1] TxD[1] TCG[1]/TCG[6] TxD[2] TxD[2] TCG[2]/TCG[7] TxD[3] TxD[3] TCG[3]/TCG[8] TCG[4]/TCG[9] TX_EN TX_CTL (TX_EN/ TX_ERR) TX_ER RX_CLK RX_CLK RX_CLK RxD[0] RxD[0]/RxD[4] RCG[0]/RCG[5] RxD[1] RxD[1]/RxD[5] RCG[1]/RCG[6] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-141...
Page 860 Signals GTX_CLK GTX_CLK TX_CLK TxD[0] TxD[0 TxD[1] TxD[1] TxD[2] TxD[2] TxD[3] TxD[3] TX_EN TX_CTL (TX_EN/TX_ERR) TX_ER RX_CLK RX_CLK RxD[0] RxD[0]/RxD[4] RxD[1] RxD[1]/RxD[5] RxD[2] RxD[2]/RxD[6] RxD[3] RxD[3]/RxD[7] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-142 Freescale Semiconductor...
Page 861 This sections describes which registers are reset due to a hard or software reset and what registers the user must initialize prior to enabling the eTSEC. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-143...
Page 862 RxBD pointed to by the RBASEn registers. If TCP/IP off-load is to be enabled, RCTRL[PRSDEP] must be set to the required off-load level. Both transmit and receive can be gracefully stopped after transmission and reception begins. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-144 Freescale Semiconductor...
Page 863 (TxBD) in TxBD ring 0 every 512 transmit clocks. If TxBD[R] is set, and the TxBD ring is scheduled for transmission, the eTSEC begins copying the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-145...
Page 864 Ethernet controller writes the frame status bits into the BD and clears TxBD[R]. If the end of the current buffer is reached and TxBD[L] is cleared (a frame is comprised of multiple buffer descriptors), only TxBD[R] is cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-146 Freescale Semiconductor...
Page 865 The RxBD length is determined by the MRBL field in the maximum receive buffer length register (MRBLR). The smallest valid value is 64 bytes, with larger values being be some integral multiple of 64 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-147...
Page 866 The first TxBD of every frame containing a custom preamble has its PRE bit set • An 8-byte custom preamble sequence appears before the Ethernet DA field in the first transmit data buffer MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-148 Freescale Semiconductor...
Page 867 The fields of the received preamble sequence are described in Table 15-145. Should the received preamble be shorter than the 7-octet sequence defined by IEEE Std. 802.3, initial bytes of the received preamble MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-149...
Page 868 15.6.2.7 Frame Recognition The Ethernet controller performs frame recognition using destination address (DA) recognition. A frame can be rejected or accepted based on the outcome. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-150 Freescale Semiconductor...
Page 869 In promiscuous mode, the eTSEC accepts all received frames regardless of DA. Note, however, that Ethernet frame filtering simply restricts the traffic seen by the receive queue filer. Therefore even in MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-151...
Page 870 {IGADDR, GADDR} set, while bits H[4:0] select a bit within the 32-bit register. For example, if H[8:5] = 7, IGADDR7 is selected, whereas H[8:5] = 9 selects GADDR1. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-152 Freescale Semiconductor...
Page 871 512-bin hash table increases, the vast majority of the hash table bits are set, preventing only a small fraction of frames from reaching memory. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-153...
Page 872 Start frame delimiter Destination address 01-80-C2-00-00-01 Multicast address reserved for use in MAC frames (or MAC station address) Source address — Length/type 88-08 Control frame type MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-154 Freescale Semiconductor...
Page 873 Because the eTSEC pre-fetches BDs, the BD table must be big enough so that there is always another empty BD to pre-fetch, otherwise a BSY error occurs. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-155...
Page 874 To avoid interrupt bandwidth congestion due to frequent, consecutive interrupts, the user may enable and configure interrupt coalescing to deliberately group frame interrupts, reducing the total number of MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-156 Freescale Semiconductor...
Page 875 25.2 ms The transmit timer threshold counter is reset to the value in TXIC[ICTT] and begins counting down on transmission of the frame following an interrupt. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-157...
Page 876 The controller terminates buffer transmission, sets TxBD[RL], closes the buffer, IEVENT[CRL], and attempts limit expired IEVENT[TXE]. Transmission resumes after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-158 Freescale Semiconductor...
Page 877 The eTSEC relies on the statistics collector block to increment the receive alignment error counter (RALN). If there is no CRC error, no error is reported. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-159...
Page 878 IPv6 extension headers would prevent eTSEC from calculating the pseudo-header checksum, software can calculate just the pseudo-header checksum in advance and supply it to the eTSEC as part of per-frame TOE configuration. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-160 Freescale Semiconductor...
Page 879 Offset + 0 TUP UDP CIP CTU NPH Offset + 2 L4OS L3OS Offset + 4 PHCS Offset + 6 VLCTL Figure 15-136. Transmit Frame Control Block MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-161...
Page 880 0 Do not attempt to capture transmission event time 1 Valid PTP_ID field. When this packet is transmitted, capture the time of transmission. Must be clear if TMR_CTRL[TE] is clear. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-162 Freescale Semiconductor...
Page 881 Rx FCB. Offset + 0 TUP CIP CTU EIP PERR Offset + 2 Offset + 4 Offset + 6 VLCTL Figure 15-137. Receive Frame Control Block MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-163...
Page 882 10 Inconsistent or unsupported L3 header sequence 11 Reserved — Reserved GPFP General-purpose filer event packet. This packet was filed based on matching a GPI rule sequence. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-164 Freescale Semiconductor...
Page 883 Walk through MPLS stack and find layer 3 protocol • Walk through VLAN stack and find layer 3 protocol • Recognition of the following ethertypes for inner layer parsing — LLC and SNAP header MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-165...
Page 884 IP recognition (v4/v6, ARP, encapsulated protocol) • IP header checksum verification • IPv4/6 over IPv4/6 (tunneling)—parse headers and find layer 4 protocol • IP layer 4 protocol/next header extraction MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-166 Freescale Semiconductor...
Page 885 RQCTRL field. The eTSEC memory map provides access to these fields by way of an address register (RQFAR) and two porthole registers (RQFCR and RQFPR). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-167...
Page 886 0) upon a filing rule match. Rejected frames occupy Rx FIFO space, but do not consume memory bus cycles. • The CMP field in RQCTRL determines how property PID is compared against RQPROP. Equality, inequality, greater-or-equal, and less-than compares are available. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-168 Freescale Semiconductor...
Page 887 (CMP = 01) or fails (CMP = 11). In this entry, RQPROP is then considered to be the assigned bit vector. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-169...
Page 888 If the timer is enabled (TMR_CTRL[TE] = 1), then the interrupt dedicated for timer events (in addition to the usual receive, transmit and error interrupts) will be asserted. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-170 Freescale Semiconductor...
Page 889 0x0000_0004 File priority 4 to ring 3 0x0000_0C09 000_100 1001 0x0000_0003 File priority 3 to ring 4 0x0000_1009 000_101 1001 0x0000_0002 File priority 2 to ring 5 0x0000_1409 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-171...
Page 890 20 and port number < 22. Entries 4 and 5 are initially set up to always fail (zero port number), and thus comprise empty entries that can be used at a later time. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-172 Freescale Semiconductor...
Page 891 TQUEUE[EN0–EN7] bits. For example, TxBD rings 3, 4, and 7 may be enabled for scheduling by setting EN3, EN4, and EN7, and clearing all other EN bits. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-173...
Page 892 = credit[0] + weight[0]; while credit[0] > 0 loop transmit_frame(0); credit[0] = credit[0] - frame_size; if ring_empty(0) then credit[0] = 0; endif endloop endif MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-174 Freescale Semiconductor...
Page 893 Rx buffer size, physical transmission time between eTSEC and far-end device and intra-device latency. Theoretically, the worst case is as follows: MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-175...
Page 894 If HW updates RBPTRn and the result matches RFBPTRn, the ring is deemed to have one BD remaining. Upon writing this BD back to memory (indicating the buffer is occupied) the ring is deemed to be full. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-176 Freescale Semiconductor...
Page 895 (using modulo arithmetic) between RBPTRn and RFBPTRn is < RQPRMn[FBTHR]. In multi-ring operation, if the free BD count of any active ring drops below the MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-177...
Page 896 Three programmable timer output pulse period phase aligned with 1588 timer clock – Maskable interrupts associated with each pulse • Separate maskable timer interrupt event register MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-178 Freescale Semiconductor...
Page 897 Edition), is shown in Figure 15-140. From this, it is clear that the end of the SFD is the critical point in the MII data stream. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-179...
Page 898 L4P-RQPFR[P IP Protocol IP header 0x11 ID=1011] Source IP Address SIA-RQPFR[PI IANA defines 4 multicast IP header 26-29 D=1101] address for the PTP packet MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-180 Freescale Semiconductor...
Page 899 In memory, the TxFCB, and at least the first 16 bytes of the TxPAL must be adjacent, i.e., located in continguous memory locations, as depicted in Figure 15-142. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-181...
Page 900 TxPAL. Second TxBD[Data Length] >= FIFO_TX_THR or includes the If this condition is not true, the timestamp in TxPAL is invalid. entire frame MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-182 Freescale Semiconductor...
Page 901 Offset + 0 TUP UDP CIP CTU NPH Offset + 2 L4OS L3OS Offset + 4 PHCS Offset + 6 VLCTL/PTP_ID Figure 15-143. Transmit Frame Control Block MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-183...
Page 902 L3OS octets from the start of the frame including any custom preamble header that may be present. The maximum layer 2 header length supported is thus 255 bytes. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-184 Freescale Semiconductor...
Page 903 There is a wrap bit in the last BD that informs the eTSEC to loop back to the beginning of the BD chain. Software must initialize the TBASE and RBASE registers that point to the beginning transmit and receive BDs for eTSEC. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-185...
Page 904 (in bytes) in the first word, and the buffer pointer in the second word. Unused fields or fields written by the eTSEC must be initialized to zero. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-186 Freescale Semiconductor...
Page 905 /* choose 32-bit native type */ typedef struct txbd_struct { uint_16 flags; uint_16 length; uint_32 bufptr; } txbd; Figure 15-147. Mapping of TxBDs to a C Data Structure MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-187...
Page 906 Last in frame. Written by user. 0 The buffer is not the last in the transmit frame. 1 The buffer is the last in the transmit frame. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-188 Freescale Semiconductor...
Page 907 One or more attempts where needed to send the transmit frame. If this field is 15, then 15 or more retries were needed. The Ethernet controller updates RC after sending the buffer. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-189...
Page 908 Figure 15-148. Receive Buffer Descriptor The RxBD definition is interpreted by eTSEC hardware as if RxBDs mapped to C data structures in the manner illustrated by Figure 15-149. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-190 Freescale Semiconductor...
Page 909 M-bit to quickly determine whether the frame was destined to this station. 0 The frame was received because of an address recognition hit. 1 The frame was received because of promiscuous mode. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-191...
Page 910 Initialization/Application Information 15.7.1 Interface Mode Configuration This section describes how to configure the eTSEC in different supported interface modes. These include the following: • • RMII MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-192 Freescale Semiconductor...
Page 911 TxD[0] TxD[0] TxD[1] TxD[1] TxD[2] TxD[2] TxD[3] TxD[3] TX_EN TX_EN TX_ER TX_ER RX_CLK RX_CLK RxD[0] RxD[0] RxD[1] RxD[1] RxD[2] RxD[2] RxD[3] RxD[3] RX_DV RX_DV RX_ER RX_ER MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-193...
Page 912 MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100] Perform an MII Mgmt write cycle to the external PHY Writing to MII Mgmt Control with 16-bit data intended for the external PHY register, MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-194 Freescale Semiconductor...
Page 913 Check auto-negotiation attributes in the PHY as necessary. Clear IEVENT register, IEVENT[0000_0000_0000_0000_0000_0000_0000_0000] Initialize IMASK (Optional) IMASK[0000_0000_0000_0000_0000_0000_0000_0000] Initialize MACnADDR1/2 (Optional) MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000] Initialize GADDR n (Optional) GADDR n [0000_0000_0000_0000_0000_0000_0000_0000] Initialize RCTRL (Optional) RCTRL[0000_0000_0000_0000_0000_0000_0000_0000] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-195...
Page 914 TxD[0]/TxD[4] TxD[1] TxD[1]/TxD[5] TxD[2] TxD[2]/TxD[6] TxD[3] TxD[3]/TxD[7] TX_EN TX_CTL (TX_EN/TX_ERR) TX_ER leave unconnected RX_CLK RX_CLK RxD[0] RxD[0]/RxD[4] RxD[1] RxD[1]/RxD[5] RxD[2] RxD[2]/RxD[6] RxD[3] RxD[3]/RxD[7] RX_DV RX_CTL (RX_DV/RX_ERR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-196 Freescale Semiconductor...
Page 915 (This example has RGMII 10Mbps mode, Statistics Enable = 1) Initialize MAC Station Address, MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000] to 02608C:876543, for example. Initialize MAC Station Address, MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100] to 02608C:876543, for example. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-197...
Page 916 When MIIMIND[BUSY]=0, read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d) MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-198 Freescale Semiconductor...
Page 917 Initialize (Empty) Receive Descriptor ring and fill with empty buffers Initialize RBASE0–RBASE7, RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000] Enable Transmit Queues Initialize TQUEUE Enable Receive Queues Initialize RQUEUE Enable Rx and Tx, MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-199...
Page 918 Table 15-172. Shared RMII Signals No. of No. of eTSEC Signals GMII Signals Function Signals Signals MDIO MDIO Management interface I/O Management interface clock TX_CLK REF_CLK Reference clock MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-200 Freescale Semiconductor...
Page 919 Check to see if MII Mgmt write is complete. Read MII Mgmt Indicator register and check for Busy = 0, MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000] This indicates that the write cycle was completed. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-201...
Page 920 Setting up the MII Mgmt for a read cycle to PHY’s MII Mgmt register (write the PHY’s address and Register address), MIIMADD[0000_0000_0000_0000_0000_0010_0000_0010] the PHY Status control register is at address 0x2 and lets say the PHY Address is 0x2 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-202 Freescale Semiconductor...
Page 921 Initialize (Empty) Receive Descriptor ring and fill with empty buffers Initialize RBASE0–RBASE7, RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000] Enable Transmit Queues Initialize TQUEUE Enable Receive Queues Initialize RQUEUE Enable Rx and Tx, MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-203...
Page 922 MDIO MDIO Management interface I/O Management interface clock ECGTX_CLK125 GTX_CLK125 Reference clock Table 15-176 describes the register initializations required to configure the eTSEC in RTBI mode. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-204 Freescale Semiconductor...
Page 923 Check to see if MII Mgmt write is complete. Read MII Mgmt Indicator register and check for Busy = 0, MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000] This indicates that the write cycle was completed. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-205...
Page 924 MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_00x_x110_0000] Clear IEVENT register, IEVENT[0000_0000_0000_0000_0000_0000_0000_0000] Initialize IMASK (Optional) IMASK[0000_0000_0000_0000_0000_0000_0000_0000] Initialize MACnADDR1/2 (Optional) MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000] Initialize GADDR n (Optional) GADDR n [0000_0000_0000_0000_0000_0000_0000_0000] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-206 Freescale Semiconductor...
Page 925 MAC if the desired link speed is not 1 Gbps. Software can perform MII management cycles to determine the external PHY link speed and program ECNTRL and MACCFG2 accordingly. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-207...
Page 926 Writing to MII Mgmt Control with 16-bit data intended for TBICON register, MIIMCON[0000_0000_0000_0000_0000_0000_0010_0000] This sets TBI in single clock mode and MII Mode off to enable communication with SerDes. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-208 Freescale Semiconductor...
Page 927 When MIIMIND[BUSY] = 0, read the MII Mgmt AN Expansion register and check bits 13 and 14 (NP Able and Page Rx’d) MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 15-209...
Page 928 Initialize (Empty) Receive Descriptor ring and fill with empty buffers Initialize RBASE0–RBASE7, RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000] Enable Transmit Queues Initialize TQUEUE Enable Receive Queues Initialize RQUEUE Enable Rx and Tx, MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101] MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 15-210 Freescale Semiconductor...
Page 929 The following documents are available from the ULPI web page at http://www.ulpi.org/. • UTMI+ Specification, Revision 1.0 • UTMI Low Pin-Count Interface (ULPI) Specification, Revision 1.0 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-1...
Page 930 16.1.2 Features The USB DR module includes the following features: • Complies with USB specification rev 2.0 • Supports operation as a standalone USB host controller MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-2 Freescale Semiconductor...
Page 931 ULPI—Use as USBDR_D5USB_RBIAS USBDR_D6_SER_RCV ULPI—Use as USBDR_D6USB_PLL_PWR3 USBDR_D7_DRVVBUS ULPI—Use as USBDR_D7USB_PLL_GND USBDR_DIR_DPPULLUP ULPI—Use as USBDR_DIRUSB_PLL_PWR1 USBDR_STP_SUSPEND ULPI—Use as USBDR_STPUSB_VSSA_BIAS USBDR_PWRFAULT ULPI—Use as USBDR_PWRFAULTUSB_VDDA_BIAS USBDR_PCTL0 ULPI—Use as USBDR_PCTL0USB_VSSA MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-3...
Page 932 USB port, USBDR_NXT indicates when a new byte is available for USB port to consume. State Asserted—PHY is ready to transfer byte. Meaning Negated—PHY is not ready. Timing Synchronous to PHY_CLK. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-4 Freescale Semiconductor...
Page 933 This section provides the memory map and detailed descriptions of all USB interface registers. The memory map of the USB interface is shown in Table 16-3. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-5...
Page 934 0x0000_0000 16.3.2.20/16-36 0x2_31BC ENDPTCOMPLETE—Endpoint complete 0x0000_0000 16.3.2.21/16-37 0x2_31C0 ENDPTCTRL0—Endpoint control 0 Mixed 0x0080_0080 16.3.2.22/16-38 0x2_31C4 ENDPTCTRL1—Endpoint control 1 0x0000_0000 16.3.2.23/16-39 0x2_31C8 ENDPTCTRL2—Endpoint control 2 0x0000_0000 16.3.2.23/16-39 MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-6 Freescale Semiconductor...
Page 935 Most of these registers are defined by the EHCI specification. Registers that are not defined by the EHCI specification are noted in their descriptions. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-7...
Page 936 HCIVERSION register. Table 16-5. HCIVERSION Register Field Descriptions Bits Name Description 15–0 — EHCI revision number. Value is 0x0100 indicating version 1.0. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-8 Freescale Semiconductor...
Page 937 0 after the USBDR controller is configured as a host by writing 0x3 to USBMODE; else, the reset value is always 1. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-9...
Page 938 BCD encoding of the device controller interface. The most-significant byte of the register represents a major revision and the least-significant byte is the minor revision. Figure 16-6 shows the DCIVERSION register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-10 Freescale Semiconductor...
Page 939 Operational Registers The operational registers are comprised of dynamic control or status registers that may be read-only, read/write, or read/write-1-to-clear. The following sections define the operational registers. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-11...
Page 940 1 after the USBDR controller is configured as a host by writing 0x3 to USBMODE; else, the reset value is always 0. 0 Disabled 1 Enabled — Reserved, should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-12 Freescale Semiconductor...
Page 941 010 256 elements (1024 bytes) 011 128 elements (512 bytes) 100 64 elements (256 bytes) 101 32 elements (128 bytes) 110 16 elements (64 bytes) 111 8 elements (32 bytes) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-13...
Page 942 1 to them (indicated by a w1c in the bit’s W cell in Figure 16-9). Offset 0x2_3144 Access: Mixed — Reset All zeros ULPII — — Reset All zeros Figure 16-9. USB Status Register (USBSTS) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-14 Freescale Semiconductor...
Page 943 FS before connect, this bit will be set at an interval of 1 msec during the prelude to the connect and chirp. Software writes a 1 to this bit to clear it. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-15...
Page 944 This bit is also set by the controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-16 Freescale Semiconductor...
Page 945 Interrupt on async advance enable. When this bit is a one, and USBSTS[AAI] is a one, the controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[AAI]. Only used in host mode. 0 Disable 1 Enable MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-17...
Page 946 FRINDEX[13–3] is set to the SOF value and FRINDEX[2–0] is cleared (that is, SOF for 1 msec frame). If FRINDEX[13–3] is equal to the SOF value, FRINDEX[2–0] is incremented (that is, SOF for 125-µsec microframe.) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-18 Freescale Semiconductor...
Page 947 4-Kbyte aligned. The contents of this register are combined with the frame index register (FRINDEX) to enable the controller to step through the Periodic Frame List in sequence. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-19...
Page 948 This 32-bit register contains the address of the next asynchronous queue head to be executed by the host. Bits 4–0 of this register cannot be modified by the system software and always return zeros when read. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-20 Freescale Semiconductor...
Page 949 Section 16.3.2.8, “Current Asynchronous List Address Register (ASYNCLISTADDR),” for more information. Offset 0x2_3158 Access: Read/Write 11 10 EPBASE — Reset All zeros Figure 16-15. Endpoint List Address (ENDPOINTLISTADDR) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-21...
Page 950 = Total Packet Flight Time (send-only) packet (T = Time to fetch packet into TX FIFO up to specified level. = Total Packet Time (fetch and send) packet (T MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-22 Freescale Semiconductor...
Page 951 This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register clears the counter and this counter stops counting after reaching the maximum of 31. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-23...
Page 952 Offset 0x2_3170 Access: Mixed ULPISS ULPIWU ULPIRUN ULPIRW ULPIPORT ULPIADDR — Reset All zeros ULPIDATRD ULPIDTWR Reset All zeros Figure 16-18. ULPI Register Access (ULPI VIEWPORT) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-24 Freescale Semiconductor...
Page 953 The polling method above can be replaced with interrupts using the ULPI interrupt defined in the USBSTS and USBINTR registers. When a wakeup or read/write operation completes, the ULPI interrupt is set. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-25...
Page 954 Offset 0x2_3184 Access: Mixed PSPD — — — PFSC PHCD WKOC WKDS WLCN Reset 0 — SUSP Reset All zeros Figure 16-20. Port Status and Control (PORTSC) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-26 Freescale Semiconductor...
Page 955 This field is zero if Port Power(PP) is zero or in device mode. This bit is (OTG/host mode only) for use by an external power control circuit. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-27...
Page 956 (unlike EHCI), because the connection of FS and LS is managed by hardware. 00 SE0 10 J-state 01 K-state 11 Undefined — Reserved, should be cleared MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-28 Freescale Semiconductor...
Page 957 Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a one because a J-to-K transition detected, USBSTS[PCI] is also set. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-29...
Page 958 • This field is zero if Port Power(PP) is zero in host mode. Device mode: • The device port is always enabled. (This bit will be one.) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-30 Freescale Semiconductor...
Page 959 The status inputs are de-bounced using a 1-msec time constant. Values on the status inputs that do not persist for more than 1 msec will not cause an update of the status inputs, or cause and OTG interrupt. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-31...
Page 960 BSEIS B session end interrupt status. Set when VBus has fallen below the B session end threshold. Software must write a one to clear this bit. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-32 Freescale Semiconductor...
Page 961 VBUS charge. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. VBUS discharge. Setting this bit causes VBus to discharge through a resistor. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-33...
Page 962 10 Device controller (default for device only controller). 11 Host controller (default for host only controller). Defaults to the idle state and needs to be initialized to the desired operating mode after reset. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-34 Freescale Semiconductor...
Page 963 2. Note that these bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-35...
Page 964 This register is not defined in the EHCI specification. This register is only used in device mode. Offset 0x2_31B8 Access: Read only 16 15 ETBR ERBR — — Reset All zeros Figure 16-26. Endpoint Status (ENDPTSTATUS) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-36 Freescale Semiconductor...
Page 965 Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one will clear the corresponding bit in this register. ERCE[2] corresponds to endpoint 2. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-37...
Page 966 STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. 1 Endpoint stalled 0 Endpoint OK MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-38 Freescale Semiconductor...
Page 967 STALL until this bit is either cleared by software or automatically cleared as above. 0 Endpoint OK 1 Endpoint stalled 15–8 — Reserved, should be cleared RX endpoint enable 0 Disabled 1 Enabled MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-39...
Page 968 Offset 0x2_3400 (SNOOP1), 0x2_3404 (SNOOP2) Access: Read/Write 19 20 26 27 Snoop Address — Snoop Enables Reset All zeros Figure 16-30. Snoop 1 and Snoop 2 (SNOOP n ) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-40 Freescale Semiconductor...
Page 969 AGE_CNT_THRESH value, priority state zero is selected. If the aging counter is greater than or equal to the AGE_CNT_THRESH value, priority state one is selected. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-41...
Page 970 AGE_CNT_THRESH register and the number of csb_clk cycles that a particular transaction takes to complete. Offset 0x2_340C Access: Read/Write — pri_lvl1 pri_lvl0 Reset All zeros Figure 16-32. Priority Control (PRI_CTRL) MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-42 Freescale Semiconductor...
Page 971 Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The USB general purpose (CONTROL) register contains the general-purpose IP control register outputs and is shown in Figure 16-34. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-43...
Page 972 Reset the UTMI PHY PLL. This bit is not self clearing and must be cleared to complete the reset sequence. 0 UTMI PHY in normal operating state 1 Put UTMI PHY in reset state MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-44 Freescale Semiconductor...
Page 973 The system interface block contains all the control and status registers that allow a processor to interface to the USB DR module. These registers allow the processor to control the configuration of the module, MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-45...
Page 974 Due to pincount limitations the module only supports certain combinations of PHY interfaces and USB functionality. Refer to Table 16-38 for more information. Table 16-38. Supported PHY Interfaces Function UTMI Host/Device ULPI Host/Device/OTG MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-46 Freescale Semiconductor...
Page 975 The PERIODICLISTBASE address register is combined with the FRINDEX register to produce a memory pointer into the frame list. The periodic frame list implements a sliding window of work over time. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-47...
Page 976 The Typ field indicates the exact type of data structure being referenced by this pointer. The value encodings for the Typ field are given in Table 16-39. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-48 Freescale Semiconductor...
Page 977 This structure is used only for high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous TDs must be aligned on a 32-byte boundary. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-49...
Page 978 10 siTD (split transaction isochronous transfer descriptor) 11 FSTN (frame span traversal node) Terminate 1 Link Pointer field is not valid. 0 Link Pointer field is valid. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-50 Freescale Semiconductor...
Page 979 (relative to virtual memory), but allows the physical memory pages to be non-contiguous. Seven page pointers are provided to support the expression of eight isochronous transfers. The seven pointers allow MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-51...
Page 980 This is a 4K aligned pointer to physical memory. Corresponds to memory address bits 31–12. 11–2 — Reserved, should be cleared. These bits reserved for future use and should be cleared. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-52 Freescale Semiconductor...
Page 981 16.5.4.2 siTD Endpoint Capabilities/Characteristics DWords 1 and 2 specify static information about the full-speed endpoint, the addressing of the parent Companion Controller, and micro-frame scheduling control. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-53...
Page 982 1 Selects Page 1 pointer The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a one to a zero). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-54 Freescale Semiconductor...
Page 983 (as selected with the page indicator bit (P field)). The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a one to a zero). MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-55...
Page 984 Host controller updates (host controller writes) to stand-alone qTDs only occur during transfer retirement. References in the following bit field definitions of updates to the qTD are to the qTD portion of a queue head. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-56 Freescale Semiconductor...
Page 985 Terminate. Indicates to the host controller that there are no more valid entries in the queue. 0 Pointer is valid (points to a valid transfer element descriptor) 1 Pointer is invalid MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-57...
Page 986 Current rage. This field is used as an index into the qTD buffer pointer list. Valid values are in the range 0x0 to 0x4. The host controller is not required to write this field back when the qTD is retired. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-58 Freescale Semiconductor...
Page 987 10 SETUP Token generates token (2DH) (undefined if endpoint is an Interrupt transfer type, for example. µFrame S-mask field in the queue head is non-zero.) 11 Reserved, should be cleared MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-59...
Page 988 If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-60 Freescale Semiconductor...
Page 989 (as selected by C_Page). The host controller is not required to write this field back when the (Pages 1–4) qTD is retired. Software should ensure the reserved fields are initialized to zeros. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-61...
Page 990 QHLP Queue head horizontal link pointer. This field contains the address of the next data object to be processed in the horizontal list and corresponds to memory address signals [31:5], respectively. 4–3 — Reserved, should be cleared. These bits must be written as zeros. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-62 Freescale Semiconductor...
Page 991 (wMaxPacketSize). The maximum value this field may contain is 0x400 (1024). Head of reclamation list flag. This bit is set by system software to mark a queue head as being the head of the reclamation list. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-63...
Page 992 The value is the USB device address of the USB 2.0 hub below which the full- or low-speed device associated with this endpoint is attached. This field is used in the split-transaction protocol. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-64 Freescale Semiconductor...
Page 993 This area is characterized as an overlay because when the queue is advanced to the next queue element, the source queue element is merged onto this area. This area serves an execution cache for the transfer. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-65...
Page 994 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 offset Normal Path Link Pointer T 0x00 Back Path Link Pointer T 0x04 Figure 16-42. Frame Span Traversal Node Structure MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-66 Freescale Semiconductor...
Page 995 Controller Interface (EHCI) Specification. The EHCI specification describes the register-level interface for a host controller for the USB Revision 2.0. It includes a description of the hardware/software interface MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-67...
Page 996 USBCMD[PSE]. Note that the schedules can be turned on before the first port is reset (and enabled). Any time the USBCMD register is written, system software must ensure the appropriate bits are preserved, depending on the intended operation. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-68 Freescale Semiconductor...
Page 997 Port connect and disconnect and over-current events. Sensitivity to these events can be turned on or off by using the port control bits in the PORTSC register. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-69...
Page 998 If USBINTR[PCE] (port change interrupt enable) is a one, the host controller also generates an interrupt on the resume event. Software acknowledges the resume event interrupt by clearing the USBSTS[PCI]. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-70 Freescale Semiconductor...
Page 999 (see) then the host controller must execute from the periodic schedule before executing from the asynchronous schedule. It will only execute from the asynchronous schedule MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 Freescale Semiconductor 16-71...
Page 1000 The USB Specification Revision 2.0 requires that the frame boundaries (SOF frame number changes) of the high-speed bus and the full- and low-speed bus(es) below USB 2.0 hubs be strictly aligned. MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2 16-72 Freescale Semiconductor...

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