Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 532

Enhanced Local Bus Controller
Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM word
executed is the loop start word. Otherwise, the next RAM word executed is the one after the loop end word.
Loops can be executed sequentially but cannot be nested. Also, special care must be taken:
• LAST and LOOP must not be set together.
• Loop start word should not have an AMX change with regard to the previous word.
10.4.4.4.6 Repeat Execution of Current RAM Word (REDO)
The REDO function is useful for wait-state insertion in a long UPM routine that would otherwise need too
many RAM words. Setting the REDO bits of the RAM word to a nonzero value causes the UPM to
re-execute the current RAM word up to three more times, as defined in the REDO field of the current RAM
word.
Special care must be taken in the following cases:
• When UTA and REDO are set together, TA is asserted the number of times specified by the REDO
function.
• When NA and REDO are set together, the address is incremented the number of times specified by
the REDO function.
• When LOOP and REDO are set together, the loop mechanism works as usual and the line is
repeated according to the REDO function.
• LAST and REDO must not be set together.
• REDO should not be used within the exception routine.
10.4.4.4.7 Address Multiplexing (AMX)
Address lines can be controlled by the user-provided pattern in the UPM. The address multiplex (AMX)
bits in the RAM word can choose between driving the transaction address (AMX = 00), driving it
according to the multiplexing specified by the M
MAR (AMX = 11) on the address signals. The next address (NA) bit of the RAM word does not affect LA
signals, unless AMX = 00 and chooses the column address for NA = 1.
In all cases, LA[21:25] of the eLBC are driven by the five lsbs of the address selected by AMX, regardless
of whether the next address (NA) bit of the RAM word is used to increment the current address. The effect
of NA = 1 is visible only when AMX = 00 chooses the column address.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-84
Table 10-41. M
Request Serviced
Read single-beat cycle
Read burst cycle
Write single-beat cycle
Write burst cycle
Refresh timer expired
RUN command
MR Loop Field Use
x
Loop Field
RLF
RLF
WLF
WLF
TLF
RLF
MR[AM] field (AMX = 10), or driving the contents of
x
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