Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 268

System Configuration
Table 5-61 defines the bit fields of GTCPRn.
Bits Name
0–15 LCV Latched counter value. Corresponding timer's 16-bit latched value.
5.7.5.5 Global Timers Counter Registers (GTCNR1–GTCNR4)
Global timers counter registers (GTCNR1, GTCNR2, GTCNR3, and GTCNR4), shown in
four 16-bit, memory-mapped, read/write up-counters. A read cycle to a GTCNRn[CNV] fields yields the
current value of the appropriate timer but does not affect the counting operation. A write cycle to a
GTCNRn[CNV] field sets the register to the written value, causing its corresponding primary and
secondary prescaler counters to be reset.
Offset 0x1C(GTCNR1)
0x1E(GTCNR2)
0
R
W
Reset
Figure 5-45. Global Timers Counter Registers (GTCNR1—GTCNR4)
Table 5-62 defines the bit fields of GTCNR.
Bits Name
0–15 CNV Counter value.
Corresponding timer's 16-bit read/write up-counter value.
5.7.5.6 Global Timers Event Registers (GTEVR1–GTEVR4)
Global timers event registers (GTEVR1, GTEVR2, GTEVR3, and GTEVR4), shown in
used to report events recognized by any of the timers. On recognition of an output reference event, the
appropriate timer sets GTEVRn[REF], regardless of the corresponding GTMDRn[ORI]. The capture event
is only set if it is enabled by GTMDRn[CE]. GTEVRs appear as memory-mapped registers to users, which
can be read at any time.
GTEVRn bits are cleared by writing ones to them (writing zeros does not affect bit values). Both bits must
be reset before the timer negates the interrupt to the interrupt controller.
Offset 0x30(GTEVR1)
0x32(GTEVR2)
0
R
W
Reset
Figure 5-46. Global Timers Event Registers (GTEVR1—GTEVR4)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-60
Table 5-61. GTCPR n Bit Settings
0x2C(GTCNR3)
0x2E(GTCNR4)
Table 5-62. GTCNR Bit Settings
0x34(GTEVR3)
0x36(GTEVR4)
Description
CNV
All zeros
Description
—
All zeros
Figure 5-45, are
Access: Read/Write
15
Figure 5-46, are
Access: w1c
13 14 15
REF CAP
w1c w1c
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