Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 770

Enhanced Three-Speed Ethernet Controllers
Bits Name
25 RXF1 Receive frame event occurred on ring 1. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
26 RXF2 Receive frame event occurred on ring 2. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
27 RXF3 Receive frame event occurred on ring 3. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
28 RXF4 Receive frame event occurred on ring 4. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
29 RXF5 Receive frame event occurred on ring 5. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
30 RXF6 Receive frame event occurred on ring 6. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
31 RXF7 Receive frame event occurred on ring 7. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
15.5.3.3.3 Receive Interrupt Coalescing Register (RXIC)
The RXIC register enables and configures the operational parameters for interrupt coalescing associated
with received frames. Figure 15-24
Offset eTSEC1:0x2_4310; eTSEC2:0x2_5310
0 1 2 3
R
ICEN ICCS —
W
Reset
Table 15-29 describes the fields of the RXIC register.
Bits Name
0 ICEN Interrupt coalescing enable
0 Interrupt coalescing is disabled. Interrupts are raised as they are received.
1 Interrupt coalescing is enabled. If the eTSEC receive frame interrupt is enabled (IMASK[RXFEN] is set),
an interrupt is raised when the threshold number of frames is reached (defined by RXIC[ICFT]) or when
the threshold timer expires (determined by RXIC[ICTT]).
1 ICCS Interrupt coalescing timer clock source.
0 The coalescing timer advances count every 64 eTSEC Rx interface clocks (TSECn_GTX_CLK).
1 The coalescing timer advances count every 64 system clocks. This mode is recommended for FIFO
operation.
2 — Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-52
Table 15-28. RSTAT Field Descriptions (continued)
describes the RXIC register.
10 11
ICFT —
Figure 15-24. RXIC Register Definition
Table 15-29. RXIC Field Descriptions
Description
15 16
All zeros
Description
Access: Read/Write
ICTT
Freescale Semiconductor
31