Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 347

128 Sets
Address Tag 0
Block 0
Block 1 Address Tag 1
Block 2 Address Tag 2
Block 3 Address Tag 3
Each cache block contains eight contiguous words from memory that are loaded from an 8-word boundary
(that is, bits A[27–31] of the effective addresses are zero); thus, a cache block never crosses a page
boundary. Misaligned accesses across a page boundary can incur a performance penalty.
The e300 core cache blocks are loaded in four beats of 64 bits each on the 64-bit data bus. The burst load
is performed as critical-double-word-first. The data cache is blocked to internal accesses until the load
completes; the instruction cache allows sequential fetching during a cache block load. In the core, the
critical-double-word is simultaneously written to the cache and forwarded to the requesting unit, thus
minimizing stalls due to load delays.
To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the
core implements the MEI protocol during normal operation of the data cache. The new data cache MESI
extension supports the additional fourth cache coherency shared state for the data cache. To support this
feature, the shared signal, shd, has been added to the bus interface. Although the MESI protocol is
supported by the e300 core, it is not implemented on MPC8313E. The following four states indicate the
state of the cache block:
• Modified—The cache block is modified with respect to system memory; that is, data for this
address is valid only in the cache and not in system memory.
• Exclusive—This cache block holds valid data that is identical to the data at this address in system
memory. No other cache has this data.
• Shared—Only available if HID2[MESISTATE] register bit is set. The address block is valid in the
cache and in at least one other cache. This block is always consistent with system memory. That is,
the shared state is shared-unmodified; there is no shared-modified state. Although the MESI
protocol is supported by the e300 core, it is not implemented on MPC8313E.
• Invalid—This cache block does not hold valid data.
Cache coherency is enforced by on-chip bus snooping logic. Because the e300 core data cache tags are
single-ported, a simultaneous load/store and snoop access represents a resource contention. The snoop
access is given first access to the tags. The load or store then occurs on the clock following the snoop.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
State
State
State
State
Figure 7-3. e300c3 Data Cache Organization
e300 Processor Core Overview
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
8 Words/Block
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