Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 6

Paragraph
Number
5.2.1 Address Translation and Mapping ............................................................................... 5-3
5.2.2 Window into Configuration Space............................................................................... 5-4
5.2.3 Local Access Windows................................................................................................ 5-4
5.2.3.1 Local Access Register Memory Map ...................................................................... 5-4
5.2.4 Local Access Register Descriptions ............................................................................ 5-6
5.2.4.1 Internal Memory Map Registers Base Address Register (IMMRBAR).................. 5-6
5.2.4.1.1
5.2.4.2 Alternate Configuration Base Address Register (ALTCBAR)................................ 5-7
5.2.4.3 LBC Local Access Window n Base Address Registers
5.2.4.3.1
5.2.4.4 LBC Local Access Window n Attributes Registers (LBLAWAR0–
5.2.4.4.1
5.2.4.5 PCI Local Access Window n Base Address Register
5.2.4.5.1
5.2.4.6 PCI Local Access Window n Attributes Registers
5.2.4.6.1
5.2.4.7 DDR Local Access Window n Base Address Registers
5.2.4.7.1
5.2.4.8 DDR Local Access Window n Attributes Registers (DDRLAWAR0–
5.2.4.8.1
5.2.5 Precedence of Local Access Windows ...................................................................... 5-14
5.2.6 Configuring Local Access Windows ......................................................................... 5-14
5.2.7 Distinguishing Local Access Windows from Other Mapping Functions .................. 5-14
5.2.8 Outbound Address Translation and Mapping Windows............................................ 5-15
5.2.9 Inbound Address Translation and Mapping Windows .............................................. 5-15
5.2.9.1 PCI Inbound Windows........................................................................................... 5-15
5.2.10 Internal Memory Map................................................................................................ 5-15
5.2.11 Accessing Internal Memory from External Masters.................................................. 5-16
5.3 System Configuration .................................................................................................... 5-16
5.3.1 System Configuration Register Memory Map........................................................... 5-16
5.3.2 System Configuration Registers ................................................................................ 5-17
5.3.2.1 System General Purpose Register Low (SGPRL) ................................................. 5-17
5.3.2.2 System General Purpose Register High (SGPRH) ................................................ 5-17
5.3.2.3 System Part and Revision ID Register (SPRIDR) ................................................. 5-18
5.3.2.3.1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
vi
Contents
Updating IMMRBAR .......................................................................................... 5-6
(LBLAWBAR0–LBLAWBAR3) ........................................................................ 5-8
LBLAWBAR0[BASE_ADDR] Reset Value ....................................................... 5-8
LBLAWAR3) ....................................................................................................... 5-9
LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value .................................... 5-9
(PCILAWBAR0–PCILAWBAR1) .................................................................... 5-10
PCILAWBAR0[BASE_ADDR] Reset Value.................................................... 5-10
(PCILAWAR0–PCILAWAR1) .......................................................................... 5-11
PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value ................................ 5-11
(DDRLAWBAR0–DDRLAWBAR1)................................................................ 5-12
DDRLAWBAR0[BASE_ADDR] Reset Value.................................................. 5-12
DDRLAWAR1).................................................................................................. 5-13
DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value............................ 5-13
SPRIDR[PARTID] Coding ................................................................................ 5-18
Title
Page
Number
Freescale Semiconductor