Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 154

Signal Descriptions
Table 3-2. MPC8313E Signal Reference by Signal Name (continued)
Name
LALE
LB_POR_CFG_BOOT
_ECC_DIS
LBCTL
LCLK[0:1]
LCS[0:3]
LDVAL
LGPL0/LFCLE
LGPL1/LFALE
LGPL2/LOE/LFRE
LGPL3/LFWP
LGPL4/LGTA/
LUPWAIT/LFRB
LGPL5
LSRCID0
LSRCID1
LSRCID2
LSRCID3
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
3-20
Functional
Description
Block
eLBC address latch eLBC
enable
Boot time ECC eLBC
checking
eLBC data buffer eLBC
control
eLBC clocks 0–1 eLBC
eLBC chip select eLBC
0–3
Memory debug data Debug
valid
eLBC UPM general eLBC
purpose line 0/Flash
command latch
enable
eLBC GP line 1/ eLBC
Flash address latch
enable
eLBC output enable/ eLBC
GP line 2/FCM read
enable
eLBC GP line 3/ eLBC
Flash write project
eLBC GP line eLBC
4/GPCM terminate
access/
UPM wait/Flash
read/busy,
open-drain shared
pin
eLBC GP line 5 eLBC
Memory debug Debug
source ID 0
Memory debug Debug
source ID 1
Memory debug Debug
source ID 2
Memory debug Debug
source ID 3
No. of Table/
I/O
Signals Page
1 O 10-2/10-5
1 1 —
1 O 10-2/10-5
2 O 10-2/10-5
4 O 10-2/10-5
1 I/O 10-2/10-5
1 O 10-2/10-5
1 O 10-2/10-5
1 O 10-2/10-5
1 O 10-2/10-5
1 I/O 10-2/10-5
1 O 10-2/10-5
1 I/O 10-2/10-5
1 I/O 10-2/10-5
1 I/O 10-2/10-5
1 I/O 10-2/10-5
Alternate
Function(s)
M1LALE
TSEC_MDC
—
—
—
GTM1_TGATE3/
GTM2_TGATE4/
GPIO29/SPIMISO
—
—
—
—
—
—
GTM1_TIN1/
GTM2_TIN2/USBDR
_DRIVE_VBUS
GTM1_TGATE1/
GTM2_TGATE2/
USBDR_DRIVE_
VBUS
GTM1_TOUT1/
USBDR_PCTL0
LBC_PM_REF_10/
USBDR_PCTL1
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