Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 15

Paragraph
Number
10.3.1.22 Flash Byte Count Register (FBCR) ..................................................................... 10-39
10.3.1.23 Flash ECC Blockn Register (FECC0–FECC3) ................................................... 10-39
10.4 Functional Description................................................................................................. 10-40
10.4.1 Basic Architecture.................................................................................................... 10-41
10.4.1.1 Address and Address Space Checking ................................................................ 10-41
10.4.1.2 External Address Latch Enable Signal (LALE) .................................................. 10-41
10.4.1.3 Data Transfer Acknowledge (TA) ....................................................................... 10-43
10.4.1.4 Data Buffer Control (LBCTL)............................................................................. 10-44
10.4.1.5 Atomic Operation ................................................................................................ 10-44
10.4.1.6 Bus Monitor ......................................................................................................... 10-44
10.4.2 General-Purpose Chip-Select Machine (GPCM)..................................................... 10-45
10.4.2.1 GPCM Read Signal Timing ................................................................................. 10-46
10.4.2.2 GPCM Write Signal Timing ................................................................................ 10-47
10.4.2.3 Chip-Select Assertion Timing ............................................................................. 10-49
10.4.2.3.1
10.4.2.3.2
10.4.2.3.3
10.4.2.3.4
10.4.2.3.5
10.4.2.4 External Access Termination (LGTA) ................................................................. 10-55
10.4.2.5 GPCM Boot Chip-Select Operation .................................................................... 10-56
10.4.3 Flash Control Machine (FCM) ................................................................................ 10-57
10.4.3.1 FCM Buffer RAM ............................................................................................... 10-59
10.4.3.1.1
10.4.3.1.2
10.4.3.1.3
10.4.3.2 Programming FCM.............................................................................................. 10-62
10.4.3.2.1
10.4.3.2.2
10.4.3.2.3
10.4.3.2.4
10.4.3.2.5
10.4.3.3 FCM Signal Timing ............................................................................................. 10-65
10.4.3.3.1
10.4.3.3.2
10.4.3.3.3
10.4.3.3.4
10.4.3.3.5
10.4.3.4 FCM Boot Chip-Select Operation ....................................................................... 10-69
10.4.3.4.1
10.4.3.4.2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Contents
Programmable Wait State Configuration......................................................... 10-50
Chip-Select and Write Enable Negation Timing ............................................. 10-50
Relaxed Timing ............................................................................................... 10-51
Output Enable (LOE) Timing .......................................................................... 10-54
Extended Hold Time on Read Accesses .......................................................... 10-54
Buffer Layout and Page Mapping for Small-Page NAND Flash Devices ...... 10-59
Buffer Layout and Page Mapping for Large-Page NAND Flash Devices ...... 10-60
Error Correcting Codes and the Spare Region ................................................ 10-61
FCM Command Instructions ........................................................................... 10-63
FCM No-Operation Instruction ....................................................................... 10-64
FCM Address Instructions............................................................................... 10-64
FCM Data Read Instructions ........................................................................... 10-64
FCM Data Write Instructions .......................................................................... 10-65
FCM Chip-Select Timing ................................................................................ 10-65
FCM Command, Address, and Write Data Timing ......................................... 10-66
FCM Ready/Busy Timing................................................................................ 10-67
FCM Read Data Timing .................................................................................. 10-68
FCM Extended Read Hold Timing.................................................................. 10-69
FCM Bank 0 Reset Initialization ..................................................................... 10-70
Boot Block Loading into the FCM Buffer RAM............................................. 10-70
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