Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 851

Table 15-135 describes the fields of the JD register.
Bits Name
0 Jitter Enable Jitter enable. This bit is cleared by default.
0 Normal transmit operation.
1 Enable the TBI to transmit the jitter test patterns defined in IEEE 802.3z 36A.
1–3 Jitter Select Selects the jitter pattern to be transmitted in diagnostics mode. Encoding of this field is shown in the
following table. Default is 00.
User defined uses custom jitter pattern, bits 6–15
High frequency (+/- D21.5)
1010101010101010101010101010101010101010...
Mixed frequency (+/- K28.5)
1111101011000001010011111010110000010100...
Low frequency
1111100000111110000011111000001111100000...
Complex pattern (10'h17c,10'h0c9,10'h0e5,10'h2a3, 10'h17c,...)
Square Wave (- K28.7)
0011111000001111100000111110000011111000...
Reserved
Reserved
4–5 — Reserved
6–15 Custom Jitter Used in conjunction with jitter (pattern) select and jitter (diagnostic) enable; set this field to the desired
Pattern custom pattern which is continuously transmitted. Its default is 0x000.
15.5.4.3.10 TBI Control Register (TBICON)
Figure 15-126 describes the definition for the TBICON register.
Offset 0x11
0 1
R
Disable
Soft_Reset —
Rx Dis
W
Reset 0 0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-135. JD Field Descriptions
Jitter Pattern Select
2 3 4
Disable
—
Tx Dis
0 0 0 0
Figure 15-126. TBI Control Register Definition
Description
6 7 8 9
AN
—
Sense
0 0 0 0
Enhanced Three-Speed Ethernet Controllers
bit[1] bit[2] bit[3]
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
10 11 12 13
MII
Clock
Mode
Select
0 1 0 0
0
1
0
1
0
1
0
1
Access: Mixed
14 15
—
0 0
15-133