Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 620

PCI Bus Interface
Offset 0x3E
7
R
W
Reset
13.3.3.23 Maximum Latency Configuration Register
Figure 13-41 shows the maximum latency configuration register fields.
Offset 0x3F
7
R
W
Reset
13.3.3.24 PCI Function Configuration Register
Figure 13-42 shows the PCI function configuration register fields.
Offset 0x44
15
R
W
Reset 0 0 0
1
Table 13-40 shows the bit settings of the PCI function configuration register.
Table 13-40. PCI Function Configuration Register Field Descriptions
Bits Name
15–6 —
5 CFG_LOCK Configuration lock. Controls access to the PCI configuration space from the PCI port. In host mode
3–4 —
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-38
Figure 13-40. Minimum Grant Configuration Register
6 5
Figure 13-41. Maximum Latency Configuration Register
—
0 0 0 0
Figure 13-42. PCI Function Configuration Register
Reserved
the PCI configuration space is always inaccessible, so this bit is not used.
Normally, this bit will be cleared in agent mode once the configuration of the PCI controller is
complete to allow an external host to access the PCI configuration space.
0 Access to the configuration spaces is permitted.
1 Any inbound PCI access to the PCI configuration space is retried.
Configuration Word Source,"
Reserved
MIN_GNT
All zeros
4 3
MAX_LAT
All zeros
6 5
CFG_
LOCK
0 0 0 1
Description
for more information on reset configuration.
2 1
Access: Read/Write
4 3 2 1
— TLTD MLTD
0 cfg 0 0
SeeSection 4.3.1.1, "Reset
Freescale Semiconductor
0
0
0
HA
cfg