Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 564

DMA/Messaging Unit
Table 12-2 describes the OMISR register.
Bits Name
31–4 — Reserved
3 ODI Outbound doorbell interrupt. This read-only bit indicates the status of the ODR bits. It is masked by
OMIMR[ODIM].
0 No outbound doorbell interrupt.
1 There is an outbound doorbell interrupt.
2 — Reserved
1 OM1I Outbound message 1 interrupt. When set, indicates that there is an outbound message 1 interrupt. Write 1
to this position to clear this bit.
0 No outbound message 1 interrupt.
1 There is an outbound message 1 interrupt.
0 OM0I Outbound message 0 interrupt. When set, indicates that there is an outbound message 0 interrupt. Write 1
to this position to clear this bit.
0 No outbound message 0 interrupt.
1 There is an outbound message 0 interrupt.
12.3.2 Outbound Message Interrupt Mask Register (OMIMR)
OMIMR contains the interrupt mask of the doorbell and message register events generated by the local
processor. OMIMR can be read from the CSB or the PCI bus, but it can be written only from the PCI bus.
Figure 12-3 shows the OMIMR.
Offset 0x034
31
R
W
Reset
Figure 12-3. Outbound Message Interrupt Mask Register (OMIMR)
Table 12-3 describes the OMIMR register.
Bits Name
31–4 — Reserved
3 ODIM Outbound doorbell interrupt mask.
0 Outbound doorbell interrupt is allowed
1 Outbound doorbell interrupt is masked
2 — Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
12-4
Table 12-2. OMISR Field Descriptions
Description
—
All zeros
Table 12-3. OMIMR Field Descriptions
Description
Access: User Read/Write
4 3 2 1
ODIM — OM1IM OM0IM
Freescale Semiconductor
0