Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 190

Reset, Clocking, and Initialization
The attributes should be programmed as follows: alternate configuration space (ACS) should be cleared
(0b0), byte enables should be all ones, and continue (CONT) should be set.
After the first 3 bytes, 4 bytes of data should hold the desired value of the reset configuration word. The
boot sequencer assumes that a big-endian address is stored in the EEPROM.
IMMRBAR value is prepended to the EEPROM address to generate the complete memory-mapped
register's address.
2
When the I C operates in reset configuration mode, the cyclic redundancy check (CRC) is ignored, as well
as any registers following the first two reset configuration words.
Figure 4-5. EEPROM Data Format for Reset Configuration Words Preload Command
Figure 4-6 shows an example of the EEPROM contents, including the preamble, reset configuration words
and additional initialization data, and CRC. In this example, it is assumed that the EEPROM contains
information additional to the reset configuration words, which should be loaded in the functional state after
the device completes its reset flow.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-24
0 1
ACS BYTE_EN
(0) (1111)
RCWLR ADDR[14:21]
RCWLR ADDR[22:29]
Reset configuration word low [0–7]
Reset configuration word low [8–15]
Reset configuration word low [16–23]
Reset configuration word low [24–31]
ACS BYTE_EN
(0) (1111)
RCWHR ADDR[14–21]
RCWHR ADDR[22–29]
Reset configuration word high [0–7]
Reset configuration word high [8–15]
Reset configuration word high [16–23]
Reset configuration word high [24–31]
4 5 6
CONT RCWLR
(1) ADDR[12–13]
CONT RCWHR
(1) ADDR[12–13]
7
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