Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 261

Table 5-55 provides detailed descriptions of the external GTM signals.
Table 5-55. GTM External Signals—Detailed Signal Descriptions
Signal I/O
TIN n
I Global timer capture control signal. Used to latch the value of the counter when a defined transition of
TIN n is sensed by the corresponding input capture edge detector.
Meaning
Timing Assertion/Negation—Asynchronous to internal bus clock. TIN n is internally synchronized to
TGATE n
I Global timer counter gate control signal. Used to gate/restart the counter when a defined transition of
TGATE n is sensed by the corresponding input capture edge detector.
Meaning
Timing Assertion/Negation—Asynchronous to internal bus clock. TGATE n is internally
TOUT n Global timer counter output signal. The GTM output a signal on the timer output pin TOUT n when the
O
reference value is reached.
Meaning
Timing Assertion/Negation—TOUT n changes occur on the rising edge of the system clock.
5.7.5 GTM Memory Map/Register Definition
The GTM programmable register map occupies 64 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All GTM registers are 8 or 16 bits wide, located on 8-bit or 16-bit address boundaries, and should only be
accessed as 8-bit or 16-bit quantities. All addresses used in this chapter are offsets from GPT Base, as
defined in Chapter 2, "Memory Map."
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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State Asserted/Negated —According to the programmed polarity by the corresponding
GTMDR n [CE]). Each timer has a 16-bit GTCPR used to latch the value of the counter
when a defined transition of TIN n is sensed by the corresponding input capture edge
detector. Upon a capture or reference event, the corresponding GTEVR bit is set and
a maskable interrupt request is issued to the interrupt controller.
the system bus clock. If TIN n meets the asynchronous input setup time, the value of
counter is captured after one system bus clock when working with the internal clock.
State Asserted/Negated—According to the programmed polarity by the corresponding
GTCFR[GMx] bits. In a reset gate mode (GTCFR[GM n ] = 0), the TGATE n pin is used
to enable/disable count. A falling TGATE n pin enables and restarts the count and a
rising edge of TGATE n disables the count. In a normal gate mode (GTCFR[GM n ] = 1),
the TGATE n have similar functionality, except the falling edge of TGATE n does not
restart the appropriate count value in GTCNR n [CNV n ].
synchronized to the system bus clock. If TGATE n meets the asynchronous input setup
time, the counter begins counting after one system bus clock when working with the
internal clock.
State Asserted/Negated—According to the programmed polarity by the corresponding
GTMDR n [OM n ].
1. Active-low pulse on TOUT n for one timer input clock cycle as defined by the
GTMDR n [ICLK n ] bits (GTMDR n [OM n ] = 1). Thus, TOUT n may be low for one general
system clock period, one general system slow go clock period, or one TIN n pin clock
cycle period.
2. Toggle the TOUT n pin (GTMDR n [OM n ] = 0). TOUT n changes occur on the rising edge of
the system clock.
Description
System Configuration
5-53