Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 248

System Configuration
5.5.5.3 Real Time Counter Prescale Register (RTPSR)
The real time counter prescale register (RTPSR), shown in
configure the RTC prescaler's value.
Offset 0x08
0
R
W
Reset
Table 5-42 defines the bit fields of RTPSR.
Bits Name
0–31 PRSC RTC prescaler bits. Select the input clock divider for the RTC counter clock. The prescaler is programmed to
divide the RTC clock input by values from 1 to 4,294,967,296. The value 0x0000 divides the clock by 1 and
0xFFFF_FFFF divides the clock by 4,294,967,296.
To accurately predict the timing of the next count, change the RTPSR[PRSC] field only when the enable bit
RTCNR[CLE] is clear. Changing the RTPSR[PRSC] bits resets the prescaler counter. System reset and the
loading of a new value into the counter both reset the prescaler counter. Clearing RTCNR[CLE] stops the
prescaler counter.
5.5.5.4 Real Time Counter Register (RTCTR)
The real time counter register (RTCTR), shown in
current value in the RTC counter.
The CNTV value is not affected by reads or writes to RTCTR.
Offset 0x0C
0
R
W
Reset
Table 5-43 defines the bit fields of RTCTR.
Bits Name
0–31 CNTV RTC counter value field. RTCTR[CNTV] contains the current value of the time counter. This is a read-only
field. Writes have no effect on RTCTR[CNTV].
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-40
Figure 5-27. Real Time Counter Prescale Register (RTPSR)
Table 5-42. RTPSR Bit Settings
Figure 5-28. Real Time Counter Register (RTCTR)
Table 5-43. RTCTR Bit Settings
Figure 5-27, is a read/write register used to
PRSC
All zeros
Description
Figure 5-28, is a read-only register that shows the
CNTV
All zeros
Description
Access: Read/Write
31
Access: Read only
31
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