Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 53

Figure
Number
16-42 Frame Span Traversal Node Structure ................................................................................ 16-66
16-43 Derivation of Pointer into Frame List Array....................................................................... 16-72
16-44 General Format of Asynchronous Schedule List ................................................................ 16-72
16-45 Frame Boundary Relationship Between HS Bus and FS/LS Bus ....................................... 16-73
16-46 Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries .............. 16-74
16-47 Example Periodic Schedule ................................................................................................ 16-76
16-48 Example Association of iTDs to Client Request Buffer ..................................................... 16-79
16-49 Generic Queue Head Unlink Scenario ................................................................................ 16-84
16-50 Asynchronous Schedule List with Annotation to Mark Head of List................................. 16-85
16-51 Example Mapping of qTD Buffer Pointers to Buffer Pages ............................................... 16-87
16-52 Host Controller Asynchronous Schedule Split-Transaction State Machine ....................... 16-90
16-53 Split Transaction, Interrupt Scheduling Boundary Conditions ........................................... 16-93
16-54 General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading .................... 16-94
16-55 Example Host Controller Traversal of Recovery Path via FSTNs...................................... 16-96
16-56 Split Transaction State Machine for Interrupt..................................................................... 16-99
16-57 Split Transaction, Isochronous Scheduling Boundary Conditions ................................... 16-105
16-58 siTD Scheduling Boundary Examples .............................................................................. 16-107
16-59 Split Transaction State Machine for Isochronous ............................................................. 16-110
16-60 Endpoint Queue Head Organization ................................................................................. 16-123
16-61 Endpoint Queue Head Layout........................................................................................... 16-124
16-62 Endpoint Transfer Descriptor (dTD)................................................................................. 16-126
16-63 USB 2.0 Device States ...................................................................................................... 16-130
16-64 Endpoint Queue Head Diagram ........................................................................................ 16-142
16-65 Software Link Pointers...................................................................................................... 16-144
16-66 ULPI Timing ..................................................................................................................... 16-154
16-67 Sending of RX CMD......................................................................................................... 16-155
16-68 ULPI Data Transmit (NOPID) .......................................................................................... 16-155
16-69 ULPI Data Transmit (PID)................................................................................................ 16-155
16-70 ULPI Data Receive ........................................................................................................... 16-156
16-71 ULPI Register Write.......................................................................................................... 16-156
16-72 ULPI Register Read .......................................................................................................... 16-156
2
17-1 I C Block Diagram................................................................................................................ 17-1
2
17-2 I Cn Address Register (I2CnADR)....................................................................................... 17-5
2
17-3 I Cn Frequency Divider Register (I2CnFDR) ...................................................................... 17-6
2
17-4 I Cn Control Register (I2CnCR)........................................................................................... 17-7
2
17-5 I Cn Status Register (I2CnSR) ............................................................................................. 17-8
2
17-6 I Cn Data Register (I2CnDR) ............................................................................................... 17-9
2
17-7 I Cn Digital Filter Sampling Rate Register (I2CnDFSRR) .................................................. 17-9
2
17-8 I C Interface Transaction Protocol...................................................................................... 17-10
17-9 EEPROM Contents ............................................................................................................. 17-17
17-10 EEPROM Data Format for One Register Preload Command............................................. 17-18
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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