Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 230

System Configuration
SICRL[Bits]
Value
Bits Group Pin Function 0
2–3 LBC LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
NOTE: CFG_LBIU_MUX_EN = 0 bypasses the register and selects function 0
4–5 UART UART_SOUT1
UART_SIN1
UART_CTS_B1
UART_RTS_B1
UART_SOUT2
UART_SIN2
UART_CTS_B2
UART_RTS_B2
6–7 SPI_A SPIMOSI
8–9 SPI_B SPIMOSO
10–11 SPI_C SPICLK
12–13 SPI_D SPISEL
14–19 Reserved
20–21 USBDR GTM1_TIN1/GTM2_TIN2
GTM1_TGATE1/GTM2_T
GATE2
GTM1_TOUT1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-22
Table 5-28. SICRL Bit Settings (continued)
0b0/0b00 0b1/0b01
Pin Function 1
MSRCID0 (DDRID)
MSRCID1 (DDRID)
MSRCID2 (DDRID)
MSRCID3 (DDRID)
MSRCID4 (DDRID)
MDVAL (DDRID)
MSRCID0 (DDRID)
MSRCID1 (DDRID)
MSRCID2 (DDRID)
MSRCID3 (DDRID)
MSRCID4 (DDRID)
MDVAL (DDRID)
GTM1_TIN3/GTM2_
TIN4
GTM1_TGATE3/GTM
2_TGATE4
GTM1_TOUT3
—
LSRCID0
LSRCID1
LSRCID2
— LSRCID3
0b10
Pin Function 2
—
—
—
—
—
—
— —
— TSEC_TMR_TRIG2
— TSEC_TMR_ALARM1 GPIO[13]
— TSEC_TMR_PP3
—
—
—
—
—
—
— —
— —
LSRCID4
LDVAL
—
— —
— —
USBDR_DRIVE_VBU
S
USBDR_PWRFAULT
USBDR_PCTL0
USBDR_PCTL1
Reset
0b11
Value
Pin Function 3
GPIO[0] 11
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[14]
— 00
—
GPIO[8]
GPIO[9]
TSEC_TMR_CLK
TSEC_TMR_GCLK
TSEC_TMR_PP1
TSEC_TMR_PP2
GPIO[28] 11
GPIO[29] 11
GPIO[30] 11
GPIO[31] 11
— 0
— 00
—
—
—
Freescale Semiconductor